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參數(shù)資料
| 型號： | HM62G36256BP-4 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8M Synchronous Fast Static RAM(256k-word x 36-bit) |
| 中文描述： | 分同步快速靜態(tài)存儲器（256k字× 36位） |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 137K |
| 代理商： | HM62G36256BP-4 |
HM62G36256 Series
8
DC Characteristics
(Ta = 0 to 70
°
C, [Tj max = 110
°
C], V
DD
= 3.3 V +10%, –5%)
Parameter
Symbol Min
Typ
Max
Unit Notes
Input leakage current
I
LI
I
LO
I
SBZZ
I
DD4
—
—
2
μ
A
μ
A
1
Output leakage current
—
—
5
2
Standby current
—
—
100
mA 3
V
operating current,
excluding output drivers
4 ns cycle
—
—
700
mA 4
V
operating current,
excluding output drivers
5 ns cycle
I
DD5
—
—
650
mA 4
Quiescent active power
supply current
I
DD2
—
—
200
mA 5
Output low voltage
V
OL
V
OH
RQ
V
SS
V
DDQ
– 0.4
150
—
V
SS
+ 0.4
V
DDQ
300
V
6
Output high voltage
—
V
6
ZQ pin connect
resistance
250
Output low current
I
OL
I
OH
(V
DDQ
/2)/[(RQ/5)–15%]
(V
DDQ
/2)/[(RQ/5–4)+15%] —
—
(V
DDQ
/2)/[(RQ/5)+15%]
(V
DDQ
/2)/[(RQ/5–4)–15%] mA 8, 9
mA 7, 9
Output high current
Notes: 1. 0
≤
Vin
≤
V
DDQ
for all input pins (except V
REF
, ZQ, M1, M2 pin).
2. 0
≤
Vout
≤
V
DDQ
, DQ in High-Z.
3. All inputs (except clock) are held at either V
IH
or V
IL
, ZZ is held at V
IH
, Iout = 0 mA, Spec is
guaranteed at 75
°
C
junction temperature.
4. Iout = 0 mA, read 50%/write 50%, V
DD
= V
DD
max, V
IN
= V
IH
or V
IL
, Frequency = minimum cycle.
5
.
Iout = 0 mA, read 50%/write 50%, V
DD
= V
DD
max, V
IN
= V
IH
or V
IL
, Frequency = 3 MHz.
6. Minimum impedance push pull output buffer mode, I
OH
= –6 mA, I
OL
= 6 mA.
7. Measured at V
OL
= 1/2 V
DDQ
.
8. Measured at V
OH
= 1/2 V
DDQ
.
9. Output buffer impedance can be programmed by terminating the ZQ pin to V
through a
precision resister (RQ). The value of RQ is five times the output impedance desired. The
allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between
150
and 300
.
If the status of ZQ pin is open, output impedance is maximum. Maximum
impedance occurs with ZQ connected to V
. The impedance update of the output driver
occurs when the SRAM is in High-Z. Write and Deselect operations will synchronously switch
the SRAM into and out of High-Z, therefore triggering an update. The user may choose to
invoke asynchronous
G
updates by providing a
G
setup and hold about the K clock to guarantee
the proper update. At power-up, the output impedance defaults to minimum impedance. It will
take 2048 cycles for the impedance to be completely updated if the programmed impedance is
much higher than minimum impedance.
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