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參數(shù)資料
| 型號： | HM62V8512CI |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Wide Temperature Range Version4 M SRAM (512-kword x 8-bit) |
| 中文描述： | 寬溫版本4 M的SRAM（512 - KWord的× 8位） |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 57K |
| 代理商： | HM62V8512CI |
HM62V8512CI Series
7
Write Cycle
HM62V8512CI
-7
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
OHZ
70
—
ns
Chip selection to end of write
60
—
ns
4
Address setup time
0
—
ns
5
Address valid to end of write
60
—
ns
Write pulse width
50
—
ns
3, 12
Write recovery time
WE
to output in high-Z
0
—
ns
6
0
30
ns
1, 2, 7
Data to write time overlap
30
—
ns
Data hold from write time
0
—
ns
Output active from output in high-Z
5
—
ns
2
Output disable to output in high-Z
Notes: 1. t
, t
and t
are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
) of a low
CS
and a low
WE
. A write begins at the later
transition of
CS
going low or
WE
going low. A write ends at the earlier transition of
CS
going high
or
WE
going high. t
WP
is measured from the beginning of write to the end of write.
4. t
CW
is measured from
CS
going low to the end of write.
5. t
AS
is measured from the address valid to the beginning of write.
6. t
WR
is measured from the earlier of
WE
or
CS
going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
8. If the
CS
low transition occurs simultaneously with the
WE
low transition or after the
WE
transition,
the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10.Dout is the read data of next address.
11.If
CS
is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12.In the write cycle with
OE
low fixed, t
WP
must satisfy the following equation to avoid a problem of
data bus contention. t
WP
t
DW
min + t
WHZ
max
0
30
ns
1, 2, 7
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