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參數(shù)資料
| 型號： | HM62V8512CLRR-5SL |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Wire To Board Header; No. of Contacts:9 RoHS Compliant: Yes |
| 中文描述： | 四米的SRAM（512 - KWord的× 8位） |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 75K |
| 代理商： | HM62V8512CLRR-5SL |
HM62V8512C Series
12
Low V
CC
Data Retention Characteristics
(Ta = –20 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions*
3
CS
≥
V
CC
– 0.2 V, Vin
≥
0 V
V
CC
= 3.0 V, Vin
≥
0 V
CS
≥
V
CC
– 0.2 V
V
CC
for data retention
Data retention current
V
DR
I
CCDR
2
—
—
V
—
0.8*
4
20*
1
μ
A
—
0.8*
4
10*
2
μ
A
Chip deselect to data retention time
t
CDR
t
R
0
—
—
ns
See retention waveform
Operation recovery time
Notes: 1. For L-version and 10
μ
A (max.) at Ta = –20 to +40
°
C.
2. For L-SL-version and 5
μ
A (max.) at Ta = –20 to +40
°
C.
3.
CS
controls address buffer,
WE
buffer,
OE
buffer, and Din buffer. In data retention mode, Vin
levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
4. Typical values are at V
CC
= 3.0 V, Ta = +25
°
C and specified loading, and not guaranteed.
5. t
RC
= read cycle time.
t
RC
*
5
—
—
ns
Low V
CC
Data Retention Timing Waveform
(
CS
Controlled)
CC
V
2.7 V
2.0 V
0 V
CS
t
CDR
t
R
CS V – 0.2 V
DR
V
Data retention mode
相關PDF資料 |
PDF描述 |
|---|---|
| HM62V8512CLRR-7 | 4 M SRAM (512-kword x 8-bit) |
| HM62V8512CLRR-7SL | 4 M SRAM (512-kword x 8-bit) |
| HM62V8512CLTT-5SL | 4 M SRAM (512-kword x 8-bit) |
| HM62V8512CLTT-7 | Octal Buffer/Driver With 3-State Outputs 20-PDIP -40 to 85 |
| HM62V8512CLTT-7SL | 4 M SRAM (512-kword x 8-bit) |
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|---|---|
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| HM62W8512BLFP-5 | 制造商:HITACHI 功能描述: |
| HM62W8512BLTTI7 | 制造商:Hitachi 功能描述: |
| HM-630 | 制造商:Black Box Corporation 功能描述:FACE PLATE:HM-STAINLESS |
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