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參數(shù)資料
| 型號： | HM62W8128LFP-10 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 100 ns, PDSO32 |
| 封裝： | 0.525 INCH, PLASTIC, SOP-32 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 84K |
| 代理商： | HM62W8128LFP-10 |
HM62W8128 Series
10
Write Cycle
HM62W8128-10
HM62W8128-12
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t
WC
100
—
120
—
ns
Chip selection to end of write
t
CW
90
—
110
—
ns
Address setup time
t
AS
0—
0
—
ns
Address valid to end of write
t
AW
90
—
110
—
ns
Write pulse width
t
WP
80
—
100
—
ns
Write recovery time
t
WR
0—
0
—
ns
Write to output in high-Z
t
WHZ
0
40
0
50
ns
10
Data to write time overlap
t
DW
50
—
60
—
ns
Write hold from write time
t
DH
0—
0
—
ns
Output active from end of write
t
OW
10
—
10
—
ns
10
Output disable to output in High-Z
t
OHZ
0
40
0
50
ns
Notes: 1. A write occures during the overlap of a low
CS1, a high CS2, and a low WE. A write begins at the
latest transition among
CS1 going low, CS2 going high, and WE going low. A write ends at the
earliest transition among
CS1 going high, CS2 going low, and WE going high. t
WP is measured
from the beginning of write to the end of write.
2. t
CW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. t
AS is measured from the address valid to the beginning of write.
4. t
WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
5. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase
to the outputs must not be applied.
6. This parameter is sampled and not 100% tested.
7. In the cycle with
OE low fixed, t
WP must satisfy the following equation to avoid a problem of data bus
contention.
t
WP ≥ tDW min + tWHZ max
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