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參數(shù)資料
| 型號(hào)： | HM62Y16258BLTT-10SL |
| 英文描述： | x16 SRAM |
| 中文描述： | x16的SRAM |
| 文件頁數(shù)： | 13/17頁 |
| 文件大小： | 75K |
| 代理商： | HM62Y16258BLTT-10SL |
HM62Y16258B Series
13
Low V
CC
Data Retention Characteristics
(Ta = 0 to +70
°
C)
Parameter
Symbol
Min
Typ
*
4
Max
Unit
Test conditions
*3
V
CC
for data retention
V
DR
2.0
—
—
V
Vin
≥
0V
(1)
CS
≥
V
CC
– 0.2 V or
(2)
LB
=
UB
≥
V
CC
– 0.2 V
CS
≤
0.2 V
V
CC
= 2.0 V, Vin
≥
0V
(1)
CS
≥
V
CC
– 0.2 V or
(2)
LB
=
UB
≥
V
CC
– 0.2 V
CS
≤
0.2 V
Data retention current
I
CCDR
*1
—
0.3
10
μ
A
I
CCDR
*2
t
CDR
—
0.3
5
μ
A
Chip deselect to data
retention time
0
—
—
ns
See retention waveform
Operation recovery time
Notes: 1. This characteristic is guaranteed only for L-version.
2. This characteristic is guaranteed only for L-SL version.
3.
CS
controls address buffer,
WE
buffer,
OE
buffer,
LB
,
UB
buffer and Din buffer. If
CS
controls data
retention mode, Vin levels (address,
WE
,
OE
,
LB
,
UB
, I/O) can be in the high impedance state. If
LB
,
UB
controls data retention mode,
LB
,
UB
must be
LB
=
UB
≥
V
– 0.2 V,
CS
must be
CS
≤
0.2
V. The other input levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
4. Typical values are at V
CC
= 2.0 V, Ta = +25C and not guaranteed.
5. t
RC
= read cycle time.
t
R
t
RC
*5
—
—
ns
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| HM63021P-34 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field/Frame/Line Memory |
| HM63021P-45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field/Frame/Line Memory |
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