參數(shù)資料
型號(hào)： HMC660LC4B
廠商： HITTITE MICROWAVE CORP
元件分類： 放大器
英文描述： 20 MHz - 4500 MHz RF/MICROWAVE WIDE BAND LOW POWER AMPLIFIER
封裝： 4 X 4 MM, ROHS COMPLIANT, SMT, 24 PIN
文件頁(yè)數(shù)： 22/22頁(yè)
文件大?。?/td> 763K
代理商： HMC660LC4B
For price, delivery, and to place orders, please contact Hittite Microwave Corporation:
20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373
Order On-line at www.hittite.com
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ESD: On-chip ESD protection networks are incorporated on the terminals, but the RF/microwave compatible interfaces
provide minimal protection and ESD precautions should be used.
Power Supply Sequencing: The recommended power supply startup sequence is Vcc2, Vcc1, VccSH, VccCLK,
(CLKDCP, CLKDCN) if biased from independent supplies. Vcc1, VccSH, VccCLK can be connected to one +5V supply
if desired.
Input Signal Drive: For best results, the inputs should be driven differentially. The input circuit has an on-chip
resistive bias-T for separating the DC and RF components of the input. The low frequency corner of the RF path is
approximately 16 MHz (Ccoupling=10 pF, Rdc=1.28 K ohm). The input can be driven single-ended but the linearity of
the device will be degraded somewhat.
Clock Input: The clock inputs should be driven differentially if possible. The device is in track-mode when (CLKP
– CLKN) is high and it is in hold-mode when (CLKP-CLKN) is low.
The T/H-mode 2nd order linearity of the device varies somewhat with clock slew rate as shown in the performance
data plots. Because of the slew rate dependence, the 2nd order linearity will vary somewhat with clock power for
sinusoidal signals. For optimal linearity, a clock zero-crossing slew rate of roughly 4 V/ns (per clock input) or more is
recommended. For sinusoidal clock inputs, this corresponds to a sinusoidal clock power per differential half-circuit
input of -3.5 dBm at 3 GHz, 0 dBm at 2 GHz, and 6 dBm at 1 GHz.
At clock frequencies lower than 1 GHz, a square wave clock will provide the best 2nd order linearity performance.
The clock input circuit has an on-chip resistive bias-T for separating the DC and RF components of the input. The low
frequency corner of the RF path is approximately 9 MHz (Ccoupling=10 pF, Rdc = 1.7 K ohm with clock DC shorted).
Outputs: The outputs should be sensed differentially for the cleanest output waveforms. The output impedance is
50Ω resistive returned to the Vcc2 supply. If the load is also 50Ω returned to the Vcc2 supply, then the Vcc2 supply
should be 5V. If the output is capacitively coupled to 50Ω then the Vcc2 supply should be 6V. The bandwidth of the
output amplifier (beyond the hold-node) is approximately 7 GHz. This produces approximately a 1 dB roll-off at the 3
dB bandwidth of the hold node (4.5 GHz) resulting in an overall track-mode 3 dB bandwidth of approximately 3.9 GHz.
Hence, the output amplitude of the sampled waveform may be somewhat larger than the track mode response at high
input frequencies due to the effect of the output amplifier bandwidth.
The output amplifier noise contribution to the total output noise is substantial. If desired, a significant reduction in
output noise can be achieved by filtering the output to a lower bandwidth than the output amplifier bandwidth of 7
GHz. This is particularly effective if operating at lower clock rates. For example, the output noise can be reduced by
approximately 4 dB if the output bandwidth is reduced by a factor of four from 7 GHz down to 1.75 GHz.
The output will have very sharp transitions at the clock edges due to the broad output amplifier bandwidth. The
user should be aware that any significant length of cable between the chip output and the load will cause frequency
response roll-off and dispersion that can produce low amplitude tails with relatively long time-constants in the settling
of the output waveform into the load. This effect is most noticeable when operating in a lab setting with output cables
of a few feet length, even with high quality cable. Output cables between the T/H and the load should be of very high
quality and 2 ft or less in length.
Reflections between the load and the device will also degrade the hold mode response. The output cable length can
be adjusted to minimize the reflection perturbations to some extent. In general, the round trip transit time of the cable
should be an integer number of clock periods to obtain the minimal reflection perturbation in the hold mode portion of
the waveform. The optimal performance is obtained when the T/H is within 50 ps or less of the load since this gives a
reflection duration equal to the approximate settling time of the device.
Application Notes
0.02 - 4.5 GHz WIDEBAND,
3 GS/s TRACK-AND-HOLD AMPLIFIER
v02.1208
HMC660LC4B
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