參數(shù)資料
型號: HPC-DEV-SYS2-E
廠商: National Semiconductor Corporation
英文描述: CABLE, COAX, RG179, BROWN, 3MM, 25M; Length, Reel (Imperial):82ft; Attenuation, 400MHz:68.90dB; Capacitance:75pF/m; Conductor make-up:7/0.102 mm; Diameter, External:3.00mm; Impedance:75R; Length, Reel (Metric):25m; Resistance, per RoHS Compliant: Yes
中文描述: 高性能通信微控制器
文件頁數(shù): 11/30頁
文件大?。?/td> 362K
代理商: HPC-DEV-SYS2-E
Pin Descriptions
(Continued)
POWER SUPPLIES
V
CC1
, V
CC2
GND
Positive Power Supply (two pins)
Ground for On-Chip Logic
DGND
Ground for Output Buffers
Note:
There are multiple electrically connected V
CC
pins on the chip, GND
and DGND are electrically isolated. All V
CC
pins and all ground pins
must be used.
CLOCK PINS
CKI
The System Clock Input
CKO
The System Clock Output (Inversion of CKI)
Pins CKI and CKO are usually connected across an external
crystal.
CK2
Clock Output (CKI divided by 2)
OTHER PINS
WO
This is an active low open drain output which
signals an illegal situation has been detected
by the WATCHDOG logic.
ST1
Bus Cycle Status Output indicates first op-
code fetch.
ST2
Bus Cycle Status Output indicates machine
states (skip and interrupt).
RESET
Active low input that forces the chip to restart
and sets the ports in a TRI-STATE mode.
RDY/HLD
Has two uses, selected by a software bit.
This pin is either a READY input to extend
the bus cycle for slower memories or a
HOLD-REQUEST input to put the bus in a
high impedance state for external DMA pur-
poses. In the second case the I4 pin can be-
come the READY input.
Connection Diagrams
Plastic and Leaded Chip Carriers
TL/DD/10422–18
Top View
See NS Package Number V68A
11
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