參數(shù)資料
型號: HPC36083
廠商: National Semiconductor Corporation
英文描述: High-Performance microControllers
中文描述: 高性能微控制器
文件頁數(shù): 4/36頁
文件大?。?/td> 467K
代理商: HPC36083
Pin Descriptions (Continued)
B14
TS3
Timer Synchronous Output
B15
RDRDY
Read Ready Output for UPI Mode
When accessing external memory four bits of port B
are used as follows
B10
ALE
Address Latch Enable Output
B11
WR
Write Output
B12
HBE
High Byte Enable OutputInput
(sampled at reset)
B15
RD
Read Output
Port I is an 8-bit input port that can be read as general
purpose inputs and is also used for the following functions
I0
I1
NMI
Nonmaskable Interrupt Input
I2
INT2
Maskable InterruptInput CaptureURD
I3
INT3
Maskable InterruptInput CaptureUWR
I4
INT4
Maskable InterruptInput Capture
I5
SI
MICROWIREPLUS Data Input
I6
RDX
UART Data Input
I7
Port D is an 8-bit input port that can be used as general
purpose digital inputs
Port P is a 4-bit output port that can be used as general
purpose data or selected to be controlled by timers 4
through 7 in order to generate frequency duty cycle and
pulse width modulated outputs
POWER SUPPLY PINS
VCC1 and
VCC2
Positive Power Supply
GND
Ground for On-Chip Logic
DGND
Ground for Output Buffers
Note
There are two electrically connected VCC pins on the chip GND and
DGND are electrically isolated Both VCC pins and both ground pins
must be used
CLOCK PINS
CKI
The Chip System Clock Input
CKO
The Chip System Clock Output (inversion of CKI)
Pins CKI and CKO are usually connected across an external
crystal
CK2
Clock Output (CKI divided by 2)
OTHER PINS
WO
This is an active low open drain output that sig-
nals an illegal situation has been detected by the
Watch Dog logic
ST1
Bus Cycle Status Output indicates first opcode
fetch
ST2
Bus Cycle Status Output
indicates machine
states (skip interrupt and first instruction cycle)
RESET
is an active low input that forces the chip to re-
start and sets the ports in a TRI-STATE mode
RDYHLD has two uses selected by a software bit It’s ei-
ther a READY input to extend the bus cycle for
slower memories or a HOLD request input to put
the bus in a high impedance state for DMA pur-
poses
NC
(no connection) do not connect anything to this
pin
EXM
External memory enable (active high) disables
internal ROM and maps it to external memory
EI
External
interrupt
with
vector
address
FFF1FFF0 (Risingfalling edge or highlow lev-
el sensitive) Alternately can be configured as
4th input capture
EXUI
External interrupt which is internally OR’ed with
the
UART
interrupt
with
vector
address
FFF3FFF2 (Active Low)
Connection Diagrams
Plastic and Ceramic Leaded Chip Carriers
TLDD8801 – 11
Top View
See NS Package Number EL68A or V68A
See Part Selection for Ordering Information
12
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