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參數(shù)資料
| 型號： | HPFC-5100D |
| 英文描述： | Tachyon TL Mass Storage Fibre Channel IC Rev 3.0 |
| 中文描述： | 商標(biāo)法的Tachyon光纖通道海量存儲集成電路活3.0 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 166K |
| 代理商： | HPFC-5100D |
Features
Second Generation Controller
IC, Based on TACHYON
Family Architecture
Supports All Fibre Channel
Topologies; Arbitrated Loop
(FC-AL) and N_Port Fabric
Attachment
Supports Both Class 3 and
Class 2 (via Software)
33 MHz, 32/64-Bit PCI
Interface
1 Gigabit/Second Fibre
Channel Rate
Full Duplex Support with
Parallel Inbound and
Outbound Processing
32/64-Bit PCI Interface,
Compliant to PCI v2.1
Complete Hardware Handling
of Entire SCSI I/O via FCP
On-Chip Assists
Full Initiator and Target
Mode Functionality
Applications
Motherboard Integration
Host-Based Adapters
Storage Sub-systems
I
2
O Designs
Description
The HPFC-5100C, Tachyon TL, is
a second-generation controller that
leverages extensive experience in
Fibre Channel, established with the
original TACHYON controller.
Tachyon TL carries forward the
HPFC-5100C
Tachyon TL
33 MHz PCI to Fibre Channel
Controller
Technical Data
assurance of interoperability and
true Fibre Channel performance.
Tachyon TL focuses on mass
storage applications for any
topology that require Class 3 and
2 (via software) and SCSI upper
layer protocol handling. Coupled
with a high performance 33 MHz,
32/64-bit PCI bus interface,
Tachyon TL provides a cost-
effective, high-performance mass
storage solution.
TACHYON Architecture
Tachyon TL continues with the
TACHYON architecture, a
complete hardware-based state
machine design. This architec-
ture does not require an addi-
tional on-board microprocessor
and therefore avoids reduced
performance issues relating to
processor cycles per second and
access time to firmware. Rather,
the TACHYON architecture is
designed to be a single chip Fibre
Channel solution.
Tachyon TL provides the highest
levels of concurrency via
numerous independent functional
blocks providing parallel
processing of data, control, and
commands. In addition, these
blocks process at hardware
speeds versus firmware speeds,
and automate the entire SCSI I/O
in hardware. The result is
minimized latency and I/O over-
head, coupled with the highest
levels of parallelism to provide
maximum I/O rates and
bandwidth.
FC-AL Features
In addition to the high-perfor-
mance architecture, Tachyon TL
offers FC-AL-1 Fibre Channel
features, such as Auto Status,
multiple I/Os in the same loop
arbitration cycle, loop map, loop
broadcast, and loop directed
reset. These features allow the
designer to achieve higher
performance in an arbitrated loop
topology.
Physical Layer
The physical layer interface is the
popular 10-bit wide specification
that allows interfacing to a low-
cost serializer/deserializer
(SerDes) IC. This is the same
physical layer interface that is
popular on Fibre Channel disk
drives today due to its quality
gigabit signaling, small form
factor, and low cost.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HPFC-5166A | Controller Miscellaneous - Datasheet Reference |
| HPFC-5000C | Tachyon Fibre Channel Interface Controller Rev 3.0 |
| HPFC-5166A | 66 MHz PCI to Fibre Channel Controller(66 MHz PCI到光纖通道控制器) |
| HPH-2540 | HIGH PROFILE PIN HEADER |
| HPH-2540-80P-1 | HIGH PROFILE PIN HEADER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HPFC-5166A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| HPFC-5166B | 制造商:Rochester Electronics LLC 功能描述: 制造商:Agilent Technologies 功能描述:Manufacturer Supplied Status Information 制造商:PMC-Sierra 功能描述: |
| HPFC-5200C | 制造商:Agilent Technologies 功能描述:Manufacturer Supplied Status Information |
| HPFC-5200D/2.3 | 制造商:Agilent Technologies 功能描述:Telecomm/Datacomm, Other |
| HPFC-5400 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Tachyon DX2 Dual Channel Fibre Channel IC |
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