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參數(shù)資料
| 型號： | HPFC-5100D |
| 英文描述： | Tachyon TL Mass Storage Fibre Channel IC Rev 3.0 |
| 中文描述： | 商標(biāo)法的Tachyon光纖通道海量存儲(chǔ)集成電路活3.0 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 166K |
| 代理商： | HPFC-5100D |
3
Fibre Channel Operation
Fibre Channel Rate
Frame Payload Size
Topology
Classes of Operation
Upper Layer Protocol
Loop Initialization
Arbitrated Loop Capabilities
Buffer-to-Buffer Credit
Physical Layer Interface
Link Diagnostics
1 Gbit/sec, 100 MBytes/sec, each direction w/full duplex support
Up to 1024 bytes
Arbitrated Loop, Public & Private, and N_Port Fabric attachment
Class 3 and Class 2 (via software)
FCP – On-chip automation for complete SCSI I/O
Completely hardware-based for high availability
Loop map, loop-directed reset, loop broadcast, loop port bypass
Four via on-chip buffers
10-bit Interface
Link status indicators, internal/external loopback, user-definable
signal pins
FC-PH, FC-AL, FC-AL2, FC-PLDA, FC-FLA, FCP 10-bit profile
Compliance
Fibre Channel Protocol (FCP)
for SCSI Features
SCSI I/O
Complete hardware-based management and processing of entire I/O
on chip, including multiple data phases
Yes, simultaneously
32,768
Up to 8,000 commands
1 or less
Status and chained commands to same AL_PA sent in same loop
tenancy
Simplified error notification and recovery
Byte-level addressability on all data buffers, inbound and outbound
Initiator & Target Mode
Maximum # of Concurrent I/Os
I/O Request Queue
Interrupts per I/O
Arbitration Avoidance Techniques
Error Recovery
Addressability
PCI
Intended compliance for future Revision 2.2
6
32-bit or 64-bit selectable; 16 to 33 MHz. Operation to 0 MHz
guaranteed by design.
132 or 264 Mbytes/second, guaranteed for length of frame, inbound
and outbound (at 64-bit, 33 MHz)
Yes
3.3 V 5 V tolerant
Yes
Zero wait state multiple cache line bursting capable up to full frame
size, configurable latency timer, 32-byte cache line, Boot BIOS
capable
DMA Channels
Width and Rate
Burst Transfer Rate
Dual Address Cycle Support
Voltage
External Sub-system ID Support
Additional PCI Features
Advanced Configuration and
Power Interface
Tachyon TL Architectural Features
Complete Hardware-Based Design
Yes, D0 and D3 power management states supported
Numerous independent functional blocks concurrently processing
inbound data, outbound data, control and commands in hardware
Six DMA channels
Automation of complete I/O on-chip in hardware
Results in lowest latency and I/O overhead and highest levels of
parallelism
Tachyon TL Specifications
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HPFC-5166A | Controller Miscellaneous - Datasheet Reference |
| HPFC-5000C | Tachyon Fibre Channel Interface Controller Rev 3.0 |
| HPFC-5166A | 66 MHz PCI to Fibre Channel Controller(66 MHz PCI到光纖通道控制器) |
| HPH-2540 | HIGH PROFILE PIN HEADER |
| HPH-2540-80P-1 | HIGH PROFILE PIN HEADER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HPFC-5166A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Controller Miscellaneous - Datasheet Reference |
| HPFC-5166B | 制造商:Rochester Electronics LLC 功能描述: 制造商:Agilent Technologies 功能描述:Manufacturer Supplied Status Information 制造商:PMC-Sierra 功能描述: |
| HPFC-5200C | 制造商:Agilent Technologies 功能描述:Manufacturer Supplied Status Information |
| HPFC-5200D/2.3 | 制造商:Agilent Technologies 功能描述:Telecomm/Datacomm, Other |
| HPFC-5400 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Tachyon DX2 Dual Channel Fibre Channel IC |
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