tR measured 50% to 90% x 2
參數(shù)資料
型號(hào): HS1-3182-9+
廠商: Intersil
文件頁(yè)數(shù): 5/7頁(yè)
文件大?。?/td> 0K
描述: IC LN-DRVR ARINC 429 16-SBDIP
標(biāo)準(zhǔn)包裝: 23
類型: 線路驅(qū)動(dòng)器,發(fā)射器
驅(qū)動(dòng)器/接收器數(shù): 2/0
電源電壓: 13.5 V ~ 16.5 V
安裝類型: 通孔
封裝/外殼: 16-CDIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-CDIP 側(cè)面銅焊
包裝: 管件
5
FN2963.3
May 30, 2008
Driver Waveforms
NOTES:
tR measured 50% to 90% x 2
tF measured 50% to 10% x 2
VIH = 5V
VOL = -4.75V to -5.25V
VIL = 0V
VOH = 4.75V to 5.25V
When the Data (A) input is in the Logic One state and the Data (B)
input is in the Logic Zero state, AOUT is equal to VREF and BOUT is
equal to -VREF. This constitutes the Output High state. Data (A) and
Data (B) both in the Logic Zero state causes both AOUT and BOUT
to be equal to 0V which designates the output Null state. Data (A) in
the Logic Zero state and Data (B) in the Logic One state causes
AOUT to be equal to -VREF and BOUT to be equal to VREF which is
the Output Low state.
Burn-In Schematic
NOTES:
R = 400
Ω ± 5%
C1 = 0.03mF ± 20%
C2 = C3 = 500pF, NPO
+V = +15.5V ± 0.5V
-V = -15.5V ± 0.5V
V1 = +5.5V ± 0.5V
A 0.0mF decoupling capacitor is required on each of the three
supply lines (+V, -V and V1) at every 3rd Burn-In socket.
Ambient Temp. Max. = +125°C.
Package = 16 Lead Side Brazed DIP.
Pulse Conditions = A & B = 6.25kHz ±10%. B is delayed one-half
cycle and in sync with A.
VIH = 2.0V Min.
VIL = 0.5V Max.
DATA (A) 0V
DATA (B) 0V
VREF
AOUT 0V
BOUT 0V
tPHL
-VREF
AOUT - BOUT
0V
DIFFERENTIAL
OUTPUT
50%
tPLH
tR
tF
2VREF
-VREF
VREF
HIGH
NULL
LOW
-2VREF
ADJ. BY
CB
ADJ. BY
CA
5V
0V
5V
0V
+4.75V TO +5.25V
-4.75V TO -5.25V
+4.75V TO +5.25V
-4.75V TO -5.25V
+9.5V TO +10.5V
NOTE: OUTPUTS UNLOADED
-9.5V TO -10.5V
V1
DATA (B)
+V
C1
GND
-V
DATA (A)
16
15
14
13
12
11
10
9
12
34
56
7
8
C3
C2
R
HS-3182
VIL
VIH
VIL
A
B
HS-3182
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