參數(shù)資料
型號: HS3140B-883
英文描述: 14-Bit Multiplying DACs
中文描述: 14位乘法數(shù)模轉(zhuǎn)換器
文件頁數(shù): 6/8頁
文件大?。?/td> 108K
代理商: HS3140B-883
Corporation
SIGNAL PROCESSING EXCELLENCE
164
Figure 4. Microprocessor Interface to SP7514/HS3140
D0
D1
D2
D3
D4
D5
D6
D7
CLK
74273
VREF
(+ 25V MAX)
LSB
15
14
13
12
11
10
9
SP7514/
7516
8
7
6
5
4
3
2
D0
D1
D2
D3
D4
D5
D6
D7
74273
CLK
MSBGND
LATCHES
ADDRESS DECODER
G2A
74LS138
G2B
C
B
A
D0
D1
D2
D3
D4
D5
D6
D7
+
200
470
3
DD
V
400
WR
BDSEL
A2
A1
A0
VDD
+
R
I01
I02
UNIPOLAR MODE
(2-QUADRANT)
6
2
3
A1
0 VOUT
(1-2
- N
)
R0S
F
Resistor R
can be added, this will parallel R
decreas-
ing the effective resistance. If C
is reduced the
bandwidth will be increased and settling time de-
creased. However a system penalty for lowering C
is
to increase noise gain. The trade-off is noise vs.
settling time. If R
is added then a large value (1
μ
F or
greater) non-polarized capacitor C
should be added
in series with R
to eliminate any DC drifts. If settling
time is not important, eliminate R
p
and C
p
, and adjust
C
f
to prevent overshoot.
Output Offset
In most applications, the output of the DAC is fed into
an amplifier to convert the DAC’s current output to
voltage. A little known and not commonly discussed
parameter is the linearity error versus offset voltage of
the output amplifier. All CMOS DAC’s must operate
into a virtual ground, i.e., the summing junction of an
op amp. Any amplifier’s offset from the amplifier will
appear as an error at the output (which can be related
to LSB’s of error).
Most all CMOS DAC’s currently available are imple-
mented using an R-2R ladder network. The formula
for nonlinearity is typically 0.67mV/mV
(not de-
rived here). However the
SP7516
has a coefficient of
only 0.065mV/mVOS. This is due to the decoding
technique described earlier. CMOS DAC applica-
tions notes (including this one) always show a poten-
tiometer used to null out the amplifier’s offset. If an
amplifier is chosen having ‘pretrimmed’ offset it may
be possible to eliminate this component. Consider the
following calculations:
HS3140
1. Using LF441A amplifier (low power - 741 pinout)
2. Specified offset: 0.5mV max
3. Temperature coefficient of input offset: 10
μ
V/
°
C max
V
OS
max (0
°
C to 70
°
C) = 0.5mV + (70
μ
V)10
= 1.2mV
Add'l nonlinearity (max.) = 1.2mV x 0.065mV/mV
=
78
μ
V (1/2 LSB @ 16 Bits)
Where: 78
μ
V = 1/2 LSB @ 16 Bits (10V range)
Via the above configuration, the
SP7514/HS3140
can be used to divide an analog signal by digital code
(i.e. for digitally controlled gain). The transfer func-
tion is given in
Table 2,
where the value of each bit is
0 or 1. Division by all “0”s is undefined and causes the
op amp to saturate.
Applications Information
Unipolar Operation
Figure 2
shows the interconnections for unipolar
operation. Connect I
and FB
as shown in diagram.
Tie I
(Pin 7), FB
(Pin 3), and FB
(Pin 1) to Ground
(Pin 8). As shown, a series resistor is recommended in
the V
supply line to limit current during ‘turn-on’.
To maintain specified linearity, external amplifiers
must be zeroed. Apply an ALL “ZEROES” digital
input and adjust R
for V
= 0
±
1mV. The
SP7514
and
HS3140
have been used successfully
with OP-07, OP-27 and LF441A. For high speed
applications the SP2525 is recommended.
Bipolar Operation
Figure 3
shows the interconnections for bipolar op-
eration. Connect I
, I
O2
, FB
, FB
, FB
as shown in
diagram. Tie LDTR to I
O2
. As shown, a series resistor
is recommended in the V
supply line to limit current
during ‘turn-on. To maintain specified linearity, exter-
nal amplifiers must be zeroed. This is best done with
V
set to zero and, the DAC register loaded with
10...0 (MSB = 1). Set R
for V
= 0. Set R
for
V
= 0. Set V
REF
to +10V and adjust R
B
for V
OUT
to be 0V.
Grounding
Connect all GND pins to system analog ground
and tie this to digital ground. All unused input pins
must be grounded.
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