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參數(shù)資料
| 型號： | HS4339ESS01H |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-bit HMCS400-Series microcomputer with large-capacity memory |
| 中文描述： | 4位HMCS400系列的大容量存儲器微機(jī) |
| 文件頁數(shù)： | 73/78頁 |
| 文件大?。?/td> | 337K |
| 代理商： | HS4339ESS01H |
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HD404339 Series
73
a. After V
CC
reaches 4.0 V at power-on.
b. After
RESET
input goes low when stop mode is cancelled.
c. After
STOPC
input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled,
RESET
or
STOPC
must be input for at least a duration of t
RC
.
When using a crystal or ceramic oscillator, consult with the manufacturer to determine what
stabilization time is required, since it will depend on the circuit constants and stray capacitance.
3. Refer to figure 56.
4. Refer to figure 57.
5. Refer to figure 58.
6. Refer to figure 59.
7. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339.
8. Applies to the HD4074339.
Serial Interface Timing Characteristics (V
CC
= 4.0 to 5.5 V, GND = 0 V, V
disp
= V
CC
– 40 V to V
CC
, T
a
=
–20 to +75
°
C, unless otherwise specified)
During Transmit Clock Output
Item
Symbol Pins
Min
Typ Max Unit Test Condition
Note
Transmit clock cycle time
t
Scyc
t
SCKH
t
SCKL
t
SCKr
t
SCKf
t
DSO
t
SSI
t
HSI
SCK
SCK
SCK
SCK
SCK
1
—
—
t
cyc
t
Scyc
t
Scyc
ns
Load shown in figure 61
1
Transmit clock high width
0.4
—
—
Load shown in figure 61
1
Transmit clock low width
0.4
—
—
Load shown in figure 61
1
Transmit clock rise time
—
—
80
Load shown in figure 61
1
Transmit clock fall time
—
—
80
ns
Load shown in figure 61
1
Serial output data delay time
SO
—
—
300
ns
Load shown in figure 61
1
Serial input data setup time
SI
100
—
—
ns
1
Serial input data hold time
SI
200
—
—
ns
1
During Transmit Clock Input
Item
Symbol
Pins
SCK
SCK
SCK
SCK
SCK
Min
Typ Max Unit Test Condition
Note
Transmit clock cycle time
t
Scyc
t
SCKH
t
SCKL
t
SCKr
t
SCKf
1
—
—
t
cyc
t
Scyc
t
Scyc
ns
1
Transmit clock high width
0.4
—
—
1
Transmit clock low width
0.4
—
—
1
Transmit clock rise time
—
—
80
1
Transmit clock fall time
—
—
80
ns
1
Serial output data delay time t
DSO
Serial input data setup time
SO
—
—
300
ns
Load shown in figure 61
1
t
SSI
t
HSI
SI
100
—
—
ns
1
Serial input data hold time
Note:
1. Refer to figure 60.
SI
200
—
—
ns
1
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