參數(shù)資料
型號(hào): HS7512
英文描述: Double-Buffered 12-Bit Multiplying DAC
中文描述: 雙緩沖12位乘法DAC
文件頁(yè)數(shù): 2/6頁(yè)
文件大小: 96K
代理商: HS7512
Corporation
SIGNAL PROCESSING EXCELLENCE
114
SPECIFICATIONS
(Typical @ 25
°
C, nominal power supply, V
REF
= +10V, unipolar, unless otherwise noted)
PARAMETER
DIGITAL INPUT
Resolution
2–Quad, Unipolar Coding
MIN.
TYP.
MAX.
UNITS
CONDITIONS
12
Bits
Binary & Comp. Binary
The input coding is comple-
mentary binary if I
02
is used.
4–Quad, Bipolar Coding
Logic Compatibility
Offset Binary
CMOS, TTL
Digital input voltage must not
exceed supply voltage or go
below –0.5V ; “0” <0.8V;
2.4V < “1”
V
DD
Input Current
Data Set-up Time
±
1
μ
A
ns
250
All strobes are level triggered.
See Timing Diagram; GBD*
All strobes are level triggered.
See Timing Diagram; GBD*
All strobes are level triggered.
See Timing Diagram; GBD*
Strobe Width
250
ns
Data Hold Time
0
ns
REFERENCE INPUT
Voltage Range
Input Impedance
ANALOG OUTPUT
Scale Factor
Scale Factor Accuracy
±
25
12
V
4
KOhms
62.5
187.5
μ
A/V
REF
±
0.4
Using the internal feedback
resistor and an external op
amp.
At 25
°
C; the output leakage
current will create an offset
voltage at the external op amps
output. It doubles every 10
°
C
temperature increase.
Output Leakage
10
nA
Output Capacitance
C
OUT
1, all inputs high
C
OUT
1, all inputs low
C
OUT
2, all inputs high
C
2, all inputs low
STATIC PERFORMANCE
Integral Linearity
SP7512BN/KN, HS3120–2
Differential Linearity
SP7512BN/KN, HS3120–2
Monotonicity
SP7512BN/KN, HS3120–2
STABILITY
Scale Factor
Integral Linearity
Differential Linearity
STABILITY
Monotonicity Temp. Range
SP7512KN
,
HS3120C
–_
SP7512BN
HS3120B
–_
80
40
40
80
pF
pF
pF
pF
±
0.015
% FSR
±
0.024
%FSR
Guaranteed to 12 bits
(T
to T
MAX
)
Note 1
2
ppm FSR/
°
C
ppm FSR/
°
C
ppm FSR/
°
C
0.2
0.2
(T
MIN
to T
MAX
)
0
+70
+85
+125
°
C
°
C
°
C
–40
–55
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