Corporation
SIGNAL PROCESSING EXCELLENCE
118
TIMING
INPUT
DATA
t2
t3
t1
t1
t2
t3
CE
LBE
MBE
HBE
LDAC
OUTPUT
t2
t4
TIME AXIS NOT TO SCALE. ALL STROBES ARE LEVEL TRIGGERED.
t
1
: Data Setup Time, Time data must be stable before strobe (byte enable/
LDAC) goes to “0”, t
1
(min) = 250ns.
t
2
: Strobe Width. t
2
(min) = 250ns. (CE, LBE, MBE, HBE, LDAC).
t
3
: Hold Time. Time data must be stable after strobe goes to “0”, t
3
= 0ns.
t
4
: Delay from LDAC to Output, t
4
= 200ns.
NOTE: Minimum common active time for CE and any byte enable is 250ns.
ORDERING INFORMATION
Model .................................................................. Monotonicity ................................. Temperature Range ........................................ Package
Double–Buffered 12–Bit Multiplying DAC
SP7512BN ...............................................................
12–Bit ......................................... –40
°
C to +85
°
C ......................................28-pin, 0.3" SOIC
SP7512KN ...............................................................
12–Bit .............................................. 0
°
C to +70
°
C ......................................28-pin, 0.3" SOIC
HS3120C–2N ...........................................................
12–Bit .............................................. 0
°
C to +70
°
C ............................ 28-pin, 0.6" Plastic DIP
HS3120C–2Q ...........................................................
12–Bit .............................................. 0
°
C to +70
°
C .................. 28-pin, 0.6" Side–Brazed DIP
HS3120B–2Q ...........................................................
12–Bit ....................................... –55
°
C to +125
°
C .................. 28-pin, 0.6" Side–Brazed DIP
HS3120B–2/883 ......................................................
12–Bit ....................................... –55
°
C to +125
°
C .................. 28-pin, 0.6" Side–Brazed DIP