參數(shù)資料
型號： HS9-82C37ARH-Q
廠商： INTERSIL CORP
元件分類： 數(shù)學(xué)處理器
英文描述： Radiation Hardened CMOS High Performance Programmable DMA Controller
中文描述： 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, CDFP42
封裝： METAL SEALED, CERAMIC, DFP-42
文件頁數(shù)： 6/28頁
文件大小： 253K
代理商： HS9-82C37ARH-Q
6
Specifications HS-82C37ARH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
VCC = +5V
±
10%, GND = 0V, AC’s Tested at Worst Case VDD, Guaranteed Over Full Operating Range.
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
TEMPERATURE
SUBGROUP
LIMITS
UNITS
MIN
MAX
DMA (MASTER) MODE
AEN HIGH from CLK LOW (S1)
Delay Time
TCLAEH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
175
ns
DMA (MASTER) MODE (Continued)
AEN LOW from CLK HIGH (SI)
Delay Time
TCHAEL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
130
ns
ADR from READ HIGH Hold
Time
TRHAX
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
TCLCL-
100
-
ns
DB from ADSTB LOW Hold
Time
TSLDZ
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
TCLCH-
18
-
ns
ADR from WRITE HIGH Hold
Time
TWHAX
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
TCLCL-
50
-
ns
DACK Valid from CLK LOW
Delay Time
TCLDAV
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
170
ns
EOP HIGH from CLK HIGH
Delay Time
TCHIPH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
170
ns
EOP LOW from CLK HIGH
Delay Time
TCHIPL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
100
ns
ADR Stable from CLK HIGH
TCHAV
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
110
ns
DB to ADSTB LOW Setup Time
TDVSL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
TCHCL
+10
-
ns
Clock HIGH Time
(Transitions 10ns)
TCHCL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
70
-
ns
Clock LOW Time
(Transitions 10ns)
TCLCH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
50
-
ns
CLK Cycle Time
TCLCL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
200
-
ns
CLK HIGH to READ or WRITE
LOW Delay
TCHRWL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
190
ns
READ HIGH from CLK HIGH
(S4) Delay Time
TCHRH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
190
ns
WRITE HIGH from CLK HIGH
(S4) Delay Time
TCHWH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
130
ns
HRQ Valid from CLK HIGH
Delay Time
TCHRQV
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
120
ns
EOP LOW to CLK LOW Setup
Time
TEPLCL
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
40
-
ns
EOP Pulse Width
TEPLEPH
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
220
-
ns
READ or WRITE Active from
CLK HIGH
TCHRWV
VDD = 4.5V
+25
o
C, +125
o
C,
-55
o
C
9, 10, 11
-
150
ns
Spec Number
518058
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