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參數(shù)資料
| 型號： | HSP3824 |
| 廠商： | Harris Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | 直接序列擴頻基帶處理器 |
| 文件頁數(shù)： | 28/41頁 |
| 文件大?。?/td> | 276K |
| 代理商： | HSP3824 |
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HSP3824
CONFIGURATION REGISTER 2 ADDRESS (08h) MODEM CONFIGURATION REGISTER C
Bit 7, 6
These control bits are used to select the number of chips per symbol used in the I and Q paths of the receiver matched
filter correlators (see table below).
Bit 5
This control bit is used to disable the CRC16 check. When this bit is set, the processor will accept the received packet
and any packet error checks have to be detected externally. The HSP3824 will remain in the receive mode until either
the carrier is lost or the network processor resets the device to the acquisition mode, or if, in modes 2 or 3, the length
times out.
Logic 1 = Disable receiver error checks.
Logic 0 = Enable receiver checks.
Bit 4, 3
These control bits are used to select the divide ratio for the demodulators receive chip clock timing.The value of N is
determined by the following equation:
Symbol Rate = MCLK/(N x Chips per symbol).
Bit 2
This control bit sets the receiver into single or dual antenna mode. The Preamble acquisition processing length and
whether the modem scans antennas is controlled by this bit. If in single antenna mode, the ANT_SEL pin reflects CR0
bit 6 otherwise it reflects the receiver’s choice of antenna.
Logic 0 = Acquisition processing is for dual antenna acquisition.
Logic 1 = Acquisition processing is for single antenna acquisition.
Bit 1, 0
These control bits are used to indicate one of the four Preamble Header modes for receiving data. Each of the modes
includes different combinations of Header fields. Users can choose the mode with the fields that are more appropriate
for their networking requirements. The Header fields that are combined to form the various modes are:
SFD field
CRC16 field
Data length field (indicates the number of data bits that follow the Header information)
Full protocol Header
CONFIGURATION REGISTER 3 ADDRESS (0Ch) MODEM CONFIGURATION REGISTER D
Bit 7
Reserved (must set to “0”).
CHIPS PER SYMBOL
BIT 7
BIT 6
11
0
0
13
0
1
15
1
0
16
1
1
MASTER CLOCK/N
BIT 4
BIT 3
N = 2
0
0
N = 4
0
1
N = 8
1
0
N = 16
1
1
INPUT MODE
BIT 1
BIT 0
RECEIVE PREAMBLE - HEADER FIELDS
0
0
0
Preamble, with SFD Field
1
0
1
Preamble, with SFD, CRC16
2
1
0
Preamble, with SFD Length, CRC16
3
1
1
Preamble, with Full Protocol Header
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HSP3824EVAL | 制造商:Harris Corporation 功能描述: |
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| HSP3824VI96S5001 | 制造商:Harris Corporation 功能描述: |
| HSP40223221 | 制造商:PARMAR 功能描述:BALLAST HPS/MH 400W 制造商:PARMAR 功能描述:BALLAST, HPS/MH, 400W |
| HSP4070C | 制造商:JLWORLD 制造商全稱:JLWORLD 功能描述:SPEAKER SOUND GENERATORS |
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