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參數(shù)資料
| 型號： | HSP43124SC-45Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 0K |
| 描述： | IC I/O FILTER SER 24BIT 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 濾波器類型： | 串行輸入/輸出 |
| 濾波器數(shù)： | 6 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
16
AC Test Load Circuit
AC Electrical Specifications
(Note 5) VCC = +4.75V to +5.25V, TA = 0oC to 70oC (Commercial)
VCC = +4.75V to +5.25V, TA = -40oC to 85oC (Industrial)
PARAMETER
SYMBOL
NOTES
45MHz
40MHz
33MHz
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
FCLK, SCLK Period
tCP
22
-
25
-
30
-
ns
FCLK, SCLK High
tCH
8
-
10
-
12
-
ns
FCLK, SCLK Low
tCL
8
-
10
-
12
-
ns
Setup Time DIN, MXIN, SYNCIN, SYNCMX to
SCLK
tDS
8-8-9
-
ns
Hold Time DIN, MXIN, SYNCIN, SYNCMX from
SCLK
tDH
0-0-0
-
ns
Setup Time FSYNC to FCLK
tSS
8-8-8
-
ns
Hold Time FSYNC from FCLK
tSH
0-0-0
-
ns
Setup Time C0-7, A0-2 to Falling Edge of WR
tWS
10
-
10
-
10
-
ns
Hold Time C0-7, A0-2 from Falling Edge of WR
tWH
3-3-3
-
ns
Setup Time A0-2 to Falling Edge of RD
tRS
10
-
10
-
10
-
ns
Hold Time A0-2 from Rising Edge of RD
tRH
0-0-0
-
ns
WR High
tWRH
10
-
10
-
12
-
ns
WR Low
tWRL
10
-
10
-
12
-
ns
RD High
tRDH
10
-
10
-
10
-
ns
RD Low to Data Valid
tRDO
-25-25
-25
ns
RD High to Output Disable
tOD
-6-6
-6
ns
FCLK to CLKOUT
tFOC
-12-13
-14
ns
CLKOUT to SYNCOUT, DOUT
tDO
-8-9
-
10
ns
Output Rise, Fall Time
tRF
Note 6
-
3
-
3
-
3
ns
NOTES:
5. AC tests performed with CL = 40pF, IOL = 5mA, and IOH = -5mA. Input reference level for FCLK and SCLK is 2.0V, all other inputs 1.5V. Test
VIH = 3.0V, VIHC = 4.0V, VIL = 0V.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.
EQUIVALENT CIRCUIT
CL (NOTE)
IOH
1.5V
IOL
DUT
SWITCH S1 OPEN FOR ICCSB AND ICCOP
S1
±
NOTE: Test head capacitance.
HSP43124
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