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參數(shù)資料
| 型號： | HT49C50 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 14/52頁 |
| 文件大?。?/td> | 318K |
| 代理商： | HT49C50 |
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HT49C50
14
August 18, 1999
Once an interrupt subroutine is serviced, other
interrupts are all blocked (by clearing the EMI
bit). This scheme may prevent any further in-
terrupt nesting. Other interrupt requests may
take place during this interval, but only the in-
terrupt request flag will be recorded. If a cer-
tain interrupt requires servicing within the
service routine, the EMI bit and the correspond-
ing bit of the INTC0 or of INTC1 may be set in
ordertoallowinterruptnesting.Oncethestackis
full, the interrupt request will not be acknowl-
edged, even if the related interrupt is enabled,
untiltheSPisdecremented.Ifimmediateservice
isdesired,thestackshouldbepreventedfrombe-
coming full.
All these interrupts can support a wake-up
function. As an interrupt is serviced, a control
transfer occurs by pushing the contents of the
PC onto the stack followed by a branch to a sub-
Register
Bit No.
Label
Function
INTC0
(0BH)
0
EMI
Control the master (global) interrupt
(1=enabled; 0=disabled)
1
EEI0
Control the external interrupt 0
(1=enabled; 0=disabled)
2
EEI1
Control the external interrupt 1
(1=enabled; 0=disabled)
3
ET0I
Control the timer/event counter 0 interrupt
(1=enabled; 0=disabled)
4
EIF0
External interrupt 0 request flag
(1=active; 0=inactive)
5
EIF1
External interrupt 1 request flag
(1=active; 0=inactive)
6
T0F
Internal timer/event counter 0 request flag
(1=active; 0=inactive)
7
Unused bit, read as 0
INTC1
(1EH)
0
ET1I
Control the timer/event counter 1 interrupt
(1=enabled; 0=disabled)
1
ETBI
Control the time base interrupt
(1=enabled; 0:disabled)
2
ERTI
Control the real time clock interrupt
(1=enabled; 0:disabled)
3
Unused bit, read as 0
4
T1F
Internal timer/event counter 1 request flag
(1=active; 0=inactive)
5
TBF
Time base request flag
(1=active; 0=inactive)
6
RTF
Real time clock request flag
(1=active; 0=inactive)
7
Unused bit, read as 0
INTC register
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