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參數(shù)資料
| 型號(hào)： | HT49C50 |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 15/52頁 |
| 文件大?。?/td> | 318K |
| 代理商： | HT49C50 |
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HT49C50
15
August 18, 1999
routine at the specified location in the ROM.
Only the contents of the PC is pushed onto the
stack. If the contents of the register or of the
status register (STATUS) is altered by the in-
terrupt service program which corrupts the de-
sired control sequence, the contents should be
saved in advance.
External interrupts are triggered by a high to
low transition of INT0 or INT1, and the related
interrupt request flag (EIF0; bit 4 of INTC0,
EIF1; bit 5 of INTC0) is set as well. After the in-
terrupt is enabled, the stack is not full, and the
external interrupt is active, a subroutine call to
location 04H or 08H occurs. The interrupt re-
quest flag (EIF0 or EIF1) and EMI bits are all
cleared to disable other interrupts.
The internal timer/event counter 0 interrupt is
initialized by setting the timer/event counter 0
interrupt request flag (T0F; bit 6 of INTC0),
which is normally caused by a timer overflow.
After the interrupt is enabled, and the stack is
not full, and the T0F bit is set, a subroutine call
to location 0CH occurs. The related interrupt
request flag (T0F) is reset, and the EMI bit is
cleared to disable further interrupts. The
timer/event counter 1 is operated in the same
manner but its related interrupt request flag is
T1F (bit 4 of INTC1) and its subroutine call lo-
cation is 10H.
The time base interrupt is initialized by setting
the time base interrupt request flag (TBF; bit 5
of INTC1), that is caused by a regular time base
signal. After the interrupt is enabled, and the
stack is not full, and the TBF bit is set, a sub-
routine call to location 14H occurs. The related
interrupt request flag (TBF) is reset and the
EMIbitisclearedtodisablefurtherinterrupts.
The real time clock interrupt is initialized by
setting the real time clock interrupt request
flag (RTF; bit 6 of INTC1), that is caused by a
regular real time clock signal. After the inter-
rupt is enabled, and the stack is not full, and
the RTF bit is set, a subroutine call to location
18H occurs. The related interrupt request flag
(RTF) is reset and the EMI bit is cleared to dis-
able further interrupts.
Duringtheexecutionofaninterruptsubroutine,
other interrupt acknowledgments are all held
until the RETI instruction is executed or the
EMI bit and the related interrupt control bit are
set both to 1 (if the stack is not full). To return
from the interrupt subroutine, RET or RETI
may be invoked. RETI sets the EMI bit and en-
ables an interrupt service, but RET does not.
Interrupts occurring in the interval between
the rising edges of two consecutive T2 pulses
are serviced on the latter of the two T2 pulses if
the corresponding interrupts are enabled. In
the case of simultaneous requests, the priori-
ties in the following table apply. These can be
masked by resetting the EMI bit.
No.
Interrupt Source
Priority Vector
a
External interrupt 0
1
04H
b
External interrupt 1
2
08H
c
Timer/event
counter 0 overflow
3
0CH
d
Timer/event
counter 1 overflow
4
10H
e
Time base
interrupt
5
14H
f
Real time clock
interrupt
6
18H
The timer/event counter 0 interrupt request
flag (T0F), external interrupt 1 request flag
(EIF1), external interrupt 0 request flag
(EIF0), enable timer/event counter 0 interrupt
bit (ET0I), enable external interrupt 1 bit
(EEI1), enable external interrupt 0 bit (EEI0),
and enable master interrupt bit (EMI) make up
of the Interrupt Control register 0 (INTC0)
which is located at 0BH in the RAM. The real
time clock interrupt request flag (RTF), time
base interrupt request flag (TBF), timer/event
counter 1 interrupt request flag (T1F), enable
real time clock interrupt bit (ERTI), and enable
time base interrupt bit (ETBI), enable
timer/event counter 1 interrupt bit (ET1I) on
the other hand, constitute the Interrupt Con-
trol register 1 (INTC1) which is located at 1EH
in the RAM. EMI, EEI0, EEI1, ET0I, ET1I,
ETBI, and ERTI are all used to control the en-
able/disable status of interrupts. These bits
prevent the requested interrupt from being ser-
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