參數(shù)資料
型號(hào): HUF76105SK8
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 功率晶體管
英文描述: 5.5A, 30V, 0.050 Ohm, N-Channel, Logic
中文描述: 5.5 A, 30 V, 0.072 ohm, N-CHANNEL, Si, POWER, MOSFET, MS-012AA
封裝: MS-012AA, 8 PIN
文件頁(yè)數(shù): 7/12頁(yè)
文件大?。?/td> 123K
代理商: HUF76105SK8
8-7
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the thermal
resistance of the heat dissipating path determines the maximum
allowable device power dissipation, P
DM
, in an application.
Therefore the application’s ambient temperature, T
A
(
o
C), and
thermalresistanceR
θ
JA
(
o
C/W)mustbereviewedtoensurethat
T
JM
is never exceeded. Equation 1 mathematically represents
the relationship and serves as the basis for establishing the rat-
ing of the part.
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power dissipation
ratings. Precise determination of P
DM
is complex and influ-
enced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms
(Continued)
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
V
DD
Q
g(TH)
Q
gs
V
GS
= 1V
Q
g(5)
V
GS
= 5V
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
Q
gd
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
(EQ. 1)
PDM
θ
JA
------------------------------
)
=
HUF76105SK8
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