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參數(shù)資料
| 型號： | HUF76407DK8 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 小信號晶體管 |
| 英文描述： | 3.5A, 60V, 0.105 Ohm, Dual N-Channel, Logic Level UltraFET Power MOSFET |
| 中文描述： | 60 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MS-012AA |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 375K |
| 代理商： | HUF76407DK8 |
7
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
application. Therefore the application’s ambient
temperature, T
A
(
o
C), and thermal resistance R
θ
JA
(
o
C/W)
must be reviewed to ensure that T
JM
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
DM
is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 23 defines the
R
θ
JA
for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
Displayed on the curve are R
θ
JA
values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P
DM
.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 23 or by calculation using
Equation 2. R
θ
JA
is defined as the natural log of the area
times a cofficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
ln
×
–
=
While Equation 2 describes the thermal resistance of a
single die, several of the new UltraFETs are offered with
two die in the SOP-8 package. The dual die SOP-8 package
introduces an additional thermal component, thermal
coupling resistance,
R
θβ
. Equation 3 describes
R
θβ
as a
function of the top copper mounting pad area.
R
θβ
46.4
21.7
Area
ln
–
=
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 23. It is important to note the
thermal resistance (R
θ
JA
) and thermal coupling resistance
(
R
θβ
) are equivalent for both die. For example at 0.1 square
inches of copper:
R
θ
JA1
= R
θ
JA2
= 159C/W
R
θβ
1
=
R
θβ
2
= 97C/W
T
J1
and T
J2
define the junction temerature of the respective
die. Similarly, P
1
and P
2
define the power dissipated in each
die. The steady state junction temperature can be calculated
using Equation 4 for die 1and Equation 5 for die 2.
Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0
Watts. The ambient temperature is 70C and the package is
mounted to a top copper area of 0.1 square inches per die.
Use Equation 4 to calulate T
J1
and and Equation 5 to
calulate T
J2
.
.
T
J1
= (0 Watts)(159C/W) + (0.5 Watts)(97C/W) + 70C
T
J1
= 119C
T
J2
= (0.5 Watts)(159C/W) + (0 Watts)(97C/W) + 70C
T
J2
= 150C
(EQ. 1)
PDM
θ
JA
–
(
------------------------------
)
=
(EQ. 2)
R
θ
JA
103.2
24.3
Area
(
)
0
0.001
50
100
150
200
250
300
0.01
0.1
1
R
θ
,
θ
J
(
o
C
AREA, TOP COPPER AREA (in
2
) PER DIE
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
191
o
C/W - 0.027in
2
228
o
C/W - 0.006in
2
R
θ
JA
= 103.2 - 24.3
*
ln
(AREA)
R
θβ
= 46.4 - 21.7
*
ln
(AREA)
(EQ. 3)
(
)
×
(EQ. 4)
TJ1
P1R
θ
JA
P2
R
θβ
TA
+
+
=
(EQ. 5)
TJ2
P2R
θ
JA
P1
R
θβ
TA
+
+
=
HUF76407DK8
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HUF76407DK8T | 功能描述:MOSFET SO-8 RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
| HUF76407DK8T_R4810 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HUF76407DK8TR4810 | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| HUF76407P3 | 功能描述:MOSFET 11a 60V 0.107 Ohm Logic Level N-Ch RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
| HUF76407P3_Q | 功能描述:MOSFET 11a 60V 0.107 Ohm Logic Level N-Ch RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
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