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參數(shù)資料
| 型號： | HY57V121620 |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 4 Banks x 8M x 16Bit Synchronous DRAM |
| 中文描述： | 4銀行× 8米× 16位同步DRAM |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 171K |
| 代理商： | HY57V121620 |
HY57V121620(L)T
4 Banks x 8M x 16Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev.0.3/Dec. 01 1
DESCRIPTION
The HY57V121620 is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large mem-
ory density and high bandwidth. HY57V121620 is organized as 4banks of 8,388,608x16.
HY57V121620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage
levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3
±
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of sys-
tem clock
Data mask function by UDQM, LDQM
Internal four banks operation
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V121620T-6
166MHz
Normal
4Banks x 8Mbits x16
LVTTL
400mil 54pin TSOP II
HY57V121620T-K
133MHz
HY57V121620T-H
133MHz
HY57V121620T-8
125MHz
HY57V121620T-P
100MHz
HY57V121620T-S
100MHz
HY57V121620LT-6
166MHz
Low power
HY57V121620LT-K
133MHz
HY57V121620LT-H
133MHz
HY57V121620LT-8
125MHz
HY57V121620LT-P
100MHz
HY57V121620LT-S
100MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V161610D-I | 2 Banks x 512K x 16 Bit Synchronous DRAM |
| HY57V161610DTC-10I | 2 Banks x 512K x 16 Bit Synchronous DRAM |
| HY57V161610ET-I | 2 Banks x 512K x 16 Bit Synchronous DRAM |
| HY57V161610DTC-55I | 2 Banks x 512K x 16 Bit Synchronous DRAM |
| HY57V161610DTC-6I | 2 Banks x 512K x 16 Bit Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V121620LT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 16Bit Synchronous DRAM |
| HY57V121620LT-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 16Bit Synchronous DRAM |
| HY57V121620LT-8 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 16Bit Synchronous DRAM |
| HY57V121620LT-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 16Bit Synchronous DRAM |
| HY57V121620LT-K | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 16Bit Synchronous DRAM |
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