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參數(shù)資料
| 型號(hào)： | HYB 39S64160AT |
| 廠商： | SIEMENS AG |
| 英文描述： | 4M x 16 MBit Synchronous DRAM for High Speed Graphics Applications(64M位(4M x 16)同步動(dòng)態(tài)RAM（用于高速圖形場(chǎng)合）) |
| 中文描述： | 4米× 16兆比特同步DRAM高速圖形應(yīng)用程序（6400位（4米× 16）同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（用于高速圖形場(chǎng)合）） |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 118K |
| 代理商： | HYB 39S64160AT |
INFINEON Technologies
3
HYB39S6416A/BT-5.5/-6/-7
64MBit Synchronous DRAM
Signal Pin Description
Pin
Type Signal Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the
rising edge of the clock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the CLK signal
when low, thereby initiates either the Power Down mode, Suspend
mode, or the Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
RAS,
CAS, WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock, CAS, RAS, and
WE define the command to be executed by the SDRAM.
A0 - A11
Input
Level
—
During a Bank Activate command cycle, A0-A11 defines the row
address (RA0-RA11) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column
address (CA0-CAn) when sampled at the rising clock edge.CAn
depends from the SDRAM organisation:
4M x 16 SDRAM CAn = CA7 (Page Length = 256 bits)
In addition to the column address, A10(=AP) is used to invoke
autoprecharge operation at the end of the burst read or write cycle. If
A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to
be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (=AP) is used in conjunction
with BA0 and BA1 to control which bank(s) to precharge. If A10 is high,
all four banks will be precharged regardless of the state of BA0 and BA1.
If A10 is low, then BA0 and BA1 are used to define which bank to
precharge.
BA0,BA1
Input
Level
—
Bank Select (BS) Inputs. Selects which bank is to be active.
DQx
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional
DRAMs.
DQM
LDQM
UDQM
Input
Pulse
Active
High
The Data Input/Output mask places the DQ buffers in a high impedance
state when sampled high. In Read mode, DQM has a latency of two
clock cycles and controls the output buffers like an output enable. In
Write mode, DQM has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the write operation
if DQM is high.
One DQM input it present in x4 and x8 SDRAMs, LDQM and UDQM
controls the lower and upper bytes in x16 SDRAMs.
VDD,VSS Supply
Power and ground for the input buffers and the core logic.
VDDQ
VSSQ
Supply
—
—
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Vref
Input
Level
—
Reference voltage for SDRAM versions supporting SSTL interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB 39S64160BT | 4M x 16 MBit Synchronous DRAM for High Speed Graphics Applications(64M位(4列 × 1M位 × 16)同步動(dòng)態(tài)RAM（用于高速圖形場(chǎng)合）) |
| HYB 39S64400BT | 64MBit Synchronous DRAM(64M位(4列 × 4M位 × 4)同步動(dòng)態(tài)RAM) |
| HYB 39S64800BT | 64MBit Synchronous DRAM(64M位(4列 × 2M位 × 8)同步動(dòng)態(tài)RAM) |
| HYB 39S64XXX0BTL | 64MBitSynchronous DRAM(64M位同步動(dòng)態(tài)RAM(低功耗版)) |
| HYB 39S64400CT | 64MBit Synchronous DRAM(64M位(4列 × 4M位 × 4)同步動(dòng)態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S64160AT-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:64 MBit Synchronous DRAM |
| HYB39S64160AT-5.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HYB39S64160AT-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HYB39S64160AT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HYB39S64160AT-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
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