參數(shù)資料
型號(hào): HYB 514171BJ-50
廠商: SIEMENS AG
英文描述: 256k × 16-Bit Dynamic RAM(256k × 16位 動(dòng)態(tài) RAM)
中文描述: 256k × 16位動(dòng)態(tài)隨機(jī)存儲(chǔ)器(256k × 16位動(dòng)態(tài)內(nèi)存)
文件頁數(shù): 6/23頁
文件大?。?/td> 181K
代理商: HYB 514171BJ-50
HYB 514171BJ-50/-60
256k
×
16 DRAM
Semiconductor Group
6
1998-10-01
Capacitance
T
A
= 0 to 70
°
C;
V
CC
= 5 V
±
10 %,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A8)
C
I1
C
I2
C
IO
6
pF
Input capacitance (RAS, UCAS, LCAS, WE, OE)
7
pF
Output capacitance (l/O1 to l/O16)
7
pF
AC Characteristics
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
CC
= 5 V
±
10 %,
t
T
= 5 ns
Parameter
5, 6
Symbol
Limit Values
Unit Note
-50
-60
min.
max.
min.
max.
Common Parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
95
110
ns
RAS precharge time
35
40
ns
RAS pulse width
50
10k
60
10k
ns
CAS pulse width
15
10k
15
10k
ns
Row address setup time
0
0
ns
Row address hold time
10
10
ns
Column address setup time
0
0
ns
Column address hold time
10
15
ns
RAS to CAS delay time
20
35
20
45
ns
RAS to column address delay time
15
25
15
30
ns
RAS hold time
15
15
ns
CAS hold time
50
60
ns
CAS to RAS precharge time
5
5
ns
Transition time (rise and fall)
3
50
3
50
ns
7
Refresh period
16
16
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
t
OEA
50
60
ns
8, 9
Access time from CAS
15
15
ns
8, 9
Access time from column address
25
30
ns
8, 10
OE access time
15
15
ns
相關(guān)PDF資料
PDF描述
HYB514171BJ-50 256k x 16-Bit Dynamic RAM
HYB514171BJ-50- 256k x 16-Bit Dynamic RAM
HYB 514171BJ-60 256k × 16-Bit Dynamic RAM(256k × 16位 動(dòng)態(tài) RAM)
HYB514171BJ-60 256k x 16-Bit Dynamic RAM
HYB 514175BJ-50 256k × 16-Bit Dynamic RAM(256k × 16位 動(dòng)態(tài) RAM)
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