參數(shù)資料
型號(hào): HYB18H1G321AF
廠商: QIMONDA
英文描述: GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM
中文描述: GDDR3顯卡內(nèi)存1千兆位GDDR3顯卡內(nèi)存
文件頁數(shù): 24/48頁
文件大?。?/td> 1406K
代理商: HYB18H1G321AF
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Internet Data Sheet
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
24
FIGURE 12
Timing of Vendor Code and Revision ID Generation on DQ[7:0]
4.2.6
Address command termination
The address and command termination is used to set the value of the internal termination resistors. The GDDR3 DRAM
supports ZQ / 4, ZQ / 2 and ZQ termination values. The mode register programming overwrites the programming during the
chip initialization.
4.2.7
Operation mode
The GDDR3 DRAM can be internally configured as two 512Mbit (2-CS mode) or one 1Gbit device (1-CS mode). The pins CS1
and A12 are only active in two, resp. 1-CS mode and act either as the chip select for the second rank, or the row-address for
the upper 4k-row-address range. If bit A2 from EMRS2 (“Merged Mode”) is set to 1 then the 2 operations mode will be inverted.
Note also that at 1000 MHz speed grade only 1-CS mode is supported.
TABLE 10
Operation Mode Function of defined Merged Mode
Operation Mode
Merged Mode = 0
Merged Mode = 1
0
1
one-CS
two-CS
two-CS
one-CS
CLK#
CLK
N/D
N/D
Com.
N/D
N/D
N/D
N/D
0
1
2
3
4
5
6
7
8
Add
A[9:0],
A11
9
10
N/D
N/D
RDQS
DQ[7:0]
A10
N/D
Add
EMRS
EMRS
tRIDon
Vendor Code and Revision ID
tRIDoff
EMRS: Extended Mode Register Set Command
Add: Address
N/D: NOP or Deselect
Don't Care
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18H1G321AF-10/11/14 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM
HYB18H256321BF 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
HYB18H256321BF-10 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
HYB18H256321BF-11 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM
HYB18H256321BF-11/12/14 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM