- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385432 > HYB18H1G321AF (QIMONDA) GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM PDF資料下載
參數(shù)資料
| 型號： | HYB18H1G321AF |
| 廠商： | QIMONDA |
| 英文描述： | GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM |
| 中文描述： | GDDR3顯卡內(nèi)存1千兆位GDDR3顯卡內(nèi)存 |
| 文件頁數(shù)： | 9/48頁 |
| 文件大?。?/td> | 1406K |
| 代理商： | HYB18H1G321AF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
HYB18H1G321AF–10/11/14
1-Gbit GDDR3
Internet Data Sheet
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
9
2.2
Mirror Function
The GDDR3 Graphics RAM provides a ball mirroring feature that is enabled by applying a logic HIGH on ball MF. This function
allows for efficient routing in a clam shell configuration.
Depending of the logic state applied on MF, the command and address signals will be assigned to different balls. The default
ball configuration (see
Figure 2
) corresponds to MF = LOW. The CS1 and A12 balls are not mirrored.
The DC level (HIGH or LOW) must be applied on the MF pin at power up and is not allowed to change after that.
Table 3
shows the ball assignment as a function of the logic state applied on MF.
BA<0:2>
Input
Bank Address Inputs:
BA select to which internal bank an ACTIVATE, READ, WRITE or PRECHARGE command is being
applied. BA are also used to distinguish between the MODE REGISTER SET and EXTENDED
MODE REGISTER SET commands.
Address Inputs:
During ACTIVATE, A0-A11 defines the row address. For READ/WRITE, A2-A7 and A9 defines the
column address, and A8 defines the auto precharge bit. If A8 is HIGH, the accessed bank is
precharged after execution of the column access. If A8 is LOW, AUTO PRECHARGE is disabled and
the bank remains active. Sampled with PRECHARGE, A8 determines whether one bank is
precharged (selected by BA<0:2>, A8 LOW) or all 8 banks are precharged (A8 HIGH). During
(EXTENDED) MODE REGISTER SET the address inputs define the register settings. A<0:11> are
sampled with the positive edge of CLK.
Address Inputs:
A12 define the MSB of the row address during an ACTIVATE in 1-CS mode.
ODT Impedance Reference:
The ZQ ball is used to control the ODT impedance.
Reset pin:
The RES pin is a
V
DDQ
CMOS input. RES is not internally terminated. When RES is at LOW state the
chip goes into full reset. The chip stays in full reset until RES goes to HIGH state. The Low to High
transition of the RES signal is used to latch the CKE value to set the value of the termination resistors
of the address and command inputs. After exiting the full reset a complete initialization is required
since the full reset sets the internal settings to default.
Mirror function pin:
The MF pin is a
V
DDQ
CMOS input. This pin must be hardwired on board either to a power or to a
ground plane. With MF set to HIGH, the command and address pins are reassigned in order to allow
for an easier routing on board for a back to back memory arrangement.
Enables Boundary Scan Functionality:
If Boundary Scan is not used PIN should be constantly connected to GND.
Voltage Reference:
V
REF
is the reference voltage input.
Power Supply:
Power and Ground for the internal logic.
I/O Power Supply:
Isolated Power and Ground for the output buffers to provide improved noise immunity.
Please do not connect No Connect and Reserved for Future Use balls.
Reserved for Alternate Rank
A<0:11>
Input
A<12>
Input
ZQ
-
RESET
Input
MF
Input
SEN
Input
V
REF
Supply
V
DD
,
V
SS
Supply
V
DDQ
,
V
SSQ
Supply
NC, RFU
RAR
-
Ball
Type
Detailed Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18H256321BF | 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H256321BF-10 | 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H256321BF-11 | 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H256321BF-12 | 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H256321BF-14 | 256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18H1G321AF-10/11/14 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM |
| HYB18H256321BF | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H256321BF-10 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H256321BF-11 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
| HYB18H256321BF-11/12/14 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit GDDR3 Graphics RAM GDDR3 Graphics RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。