參數(shù)資料
型號(hào): HYB18T1G160AF
廠商: INFINEON TECHNOLOGIES AG
英文描述: 1 Gbit DDR2 SDRAM
中文描述: 1千兆位DDR2內(nèi)存
文件頁(yè)數(shù): 33/89頁(yè)
文件大?。?/td> 1261K
代理商: HYB18T1G160AF
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 33 Rev. 1.02 May 2004
2.6.3 Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst. The delay from the
start of the command until the data from the first cell appears on the outputs is equal to the value of the read
latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the
data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent
data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to
an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is
defined by the Extended Mode Register Set (EMRS(1)).
Basic Burst Read Timing
Examples:
Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)
DQS,
DQS
DQ
DQS
DQS
t
RPRE
t
DQSQmax
t
RPST
t
DQSCK
t
AC
Dout
Dout
Dout
Dout
CLK, CLK
CLK
CLK
t
CH
t
CL
t
CK
DO-Read
t
QH
DQSQmax
t
QH
t
t
LZ
t
HZ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ A
T0
T2
T1
T3
T4
T5
T6
T7
T8
Dout A0
Dout A1
Dout A2
Dout A3
RL = 5
AL = 2
CL = 3
NOP
<= tDQSCK
CMD
DQ
BRead523
DQS,
DQS
Post CAS
CK, CK
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