參數(shù)資料
型號： HYB18T1G800AF-3S
廠商： INFINEON TECHNOLOGIES AG
英文描述： POT 1.0K OHM 1/4 SQ CERM SL ST
中文描述： 1千兆位DDR2內(nèi)存
文件頁數(shù)： 32/89頁
文件大小： 1752K
代理商： HYB18T1G800AF-3S
Page 32 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.6.2 Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory
locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst
length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address
ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst
length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or
interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst read or write
operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is pro-
grammed. For burst interruption of a read or write burst when burst length = 8 is used, see the “Burst Interruption”
section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices.
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing (decimal)
Interleave Addressing (decimal)
4
x 0 0
0, 1, 2, 3
0, 1, 2, 3
x 0 1
1, 2, 3, 0
1, 0, 3, 2
x 1 0
2, 3, 0, 1
2, 3, 0, 1
x 1 1
3, 0, 1, 2
3, 2, 1, 0
8
0 0 0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
0 0 1
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
0 1 0
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
0 1 1
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
1 0 0
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1 0 1
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
1 1 0
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
1 1 1
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Notes: 1) Page length is a function of I/O organization
256 Mb x 4 organization (CA0-CA9, CA11); Page Size = 1 kByte
128 Mb x 8 organization (CA0-CA9); Page Size = 1 kByte
64 Mb x 16 organization (CA0-CA9); Page Size = 2 kByte
2) Order of burst access for sequential addressing is “nibble-based” and therefore different from SDR
or DDR components
相關(guān)PDF資料
PDF描述
HYB18T1G800AF-5 1 Gbit DDR2 SDRAM
HYB18T1G800AFL-3 1 Gbit DDR2 SDRAM
HYB18T1G800AFL-37 1 Gbit DDR2 SDRAM
HYB18T1G800AFL-3S 1 Gbit DDR2 SDRAM
HYB18T1G800AFL-5 1 Gbit DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T1G800BF-3S 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
HYB18T256400AF-3.7 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60
HYB18T256400AF-5 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA
HYB18T256800AF-5 制造商:Infineon Technologies AG 功能描述:
HYB18T512161BF-25 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA
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