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參數(shù)資料
| 型號： | HYB18T1G800AF-3S |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | POT 1.0K OHM 1/4 SQ CERM SL ST |
| 中文描述： | 1千兆位DDR2內(nèi)存 |
| 文件頁數(shù)： | 42/89頁 |
| 文件大?。?/td> | 1752K |
| 代理商： | HYB18T1G800AF-3S |
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Page 42 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.7 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Com-
mand is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-charge
Command can be used to precharge each bank independently or all banks simultaneously. Three address bits
A10, BA0 ~ BA2 are used to define which bank to precharge when the command is issued.
Bank Selection for Precharge by Address Bits
Note: The bank address assignment is the same for activating and precharging a specific bank.
2.7.1 Burst Read Operation Followed by a Precharge
The following rules apply as long as the tRTP timing parameter - Internal Read to Precharge Command delay time
- is less or equal two clocks, which is the case for operating frequencies less or equal 266 Mhz (DDR2 400 and
533 speed sorts):
Minimum Read to Precharge command spacing to the same bank = AL + BL/2 clocks. For the earliest possible
precharge, the precharge command may be issued on the rising edge which is “Additive Latency (AL) + BL/2
clocks” after a Read Command, as long as the minimum tRAS
timing is satisfied.
A new bank active command may be issued to the same bank if the following two conditions are satisfied simulta-
neously:
(1) The RAS precharge time (tRP) has been satisfied from the clock at which the precharge begins.
(2) The RAS cycle time (tRCmin) from the previous bank activation has been satisfied.
For operating frequencies higher than 266 MHz, tRTP becomes > 2 clocks and one additional clock cycle has to
be added for the minimum Read to Precharge command spacing, which now becomes AL + BL/2 + 1 clocks.
A10
BA0
BA1
BA2
Precharge
Bank(s)
LOW
LOW
LOW
LOW
Bank 0 only
LOW
LOW
HIGH
LOW
Bank 1 only
LOW
HIGH
LOW
LOW
Bank 2 only
LOW
HIGH
HIGH
LOW
Bank 3 only
LOW
LOW
LOW
HIGH
Bank 4 only
LOW
LOW
HIGH
HIGH
Bank 5 only
LOW
HIGH
LOW
HIGH
Bank 6 only
LOW
HIGH
HIGH
HIGH
Bank 7 only
HIGH
Don’t Care
Don’t Care
Don’t Care
all banks
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| HYB18T1G800AF-5 | 1 Gbit DDR2 SDRAM |
| HYB18T1G800AFL-3 | 1 Gbit DDR2 SDRAM |
| HYB18T1G800AFL-37 | 1 Gbit DDR2 SDRAM |
| HYB18T1G800AFL-3S | 1 Gbit DDR2 SDRAM |
| HYB18T1G800AFL-5 | 1 Gbit DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
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