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參數(shù)資料
| 型號： | HYB18T256800AF-3 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256 Mbi t DDR2 SDRAM |
| 中文描述： | 256姆噸DDR2內(nèi)存 |
| 文件頁數(shù)： | 30/90頁 |
| 文件大?。?/td> | 1246K |
| 代理商： | HYB18T256800AF-3 |
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Page 30 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.6.1 Posted CAS
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2
SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the
RAS bank activate command (or any time during the RAS to CAS delay time, tRCD, period). The command is
held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the
sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a Read/Write command before the
tRCDmin, then AL greater than 0 must be written into the EMRS(1). The Write Latency (WL) is always defined as
RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS latency
(RL=AL+CL). If a user chooses to issue a Read command after the tRCDmin period, the Read Latency is also
defined as RL = AL + CL.
Examples:
Read followed by a write to the same bank, Activate to Read delay < tRCDmin:
AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
Read followed by a write to the same bank, Activate to Read delay < tRCDmin:
AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8
Activate
Bank A
tRCD
CL = 3
AL = 2
RL = AL + CL = 5
WL = RL -1 = 4
PostCAS1
CMD
DQ
DQS,
DQS
CK, CK
0
2
3
4
5
1
6
7
8
9
10
11
Dout0 Dout1 Dout2 Dout3
Din0
Din1
Din2
Din3
Bank A
Read
Write
Bank A
Activate
Bank A
tRCD
CL = 3
AL = 2
RL = AL + CL = 5
WL = RL -1 = 4
PostCAS3
CMD
DQ
DQS,
DQS
CK, CK
0
2
3
4
5
1
6
7
8
9
10
11
Bank A
Read
Write
Bank A
Din0
Din1
Din2
Din3
Dout0 Dout1 Dout2 Dout3 Dout4 Dout5 Dout6 Dout7
12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB18T256800AF-37 | 256 Mbi t DDR2 SDRAM |
| HYB18T256800AF-3S | 256 Mbi t DDR2 SDRAM |
| HYB18T256800AF-5 | 256 Mbi t DDR2 SDRAM |
| HYB18T256324F-16 | 256-Mbit GDDR3 DRAM [600MHz] |
| HYB18T256324F-20 | 256-Mbit GDDR3 DRAM [600MHz] |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
| HYB18T512400BF-3S | 制造商:Qimonda 功能描述: |
| HYB18T512800AF-3S | 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84 |
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