參數(shù)資料
型號(hào): HYB18T512400AF-5
廠商: INFINEON TECHNOLOGIES AG
英文描述: CAP.00027UF 16V PPS FILM 0603 5%
中文描述: 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁(yè)數(shù): 4/33頁(yè)
文件大小: 936K
代理商: HYB18T512400AF-5
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
Data Sheet
Preliminary
4
Rev. 0.85, 2004-04
1.3 Components on Modules and RawCard
1.4 Pin Definition and Function
DIMM
Density
DRAM components
reference datasheet
PLL
Register
Raw Card
512 MB
HYB18T512800AC
HYB18T512800AF
1:10, 1.8V, CU877
1:1 25-bit 1.8V SSTU32864
A
1024 MB
HYB18T512800AC
HYB18T512800AF
1:10, 1.8V, CU877
1:2 14-bit 1.8V SSTU32864
B
1024 MB
HYB18T512400AC
HYB18T512400AF
1:10, 1.8V, CU877
1:2 14-bit 1.8V SSTU32864
C
2048 MB
HYB18T512400AC
HYB18T512400AF
tbd.
tbd.
tbd.
2048 MB
HYB18T512400AC
HYB18T512400AF
tbd.
tbd.
tbd.
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component data
sheet
Pin Name
Description
Pin Name
Description
A[13:0]
Row Address Inputs
CB[7:0]
DIMM ECC Check Bits
A11, A[9:0]
Column Address Inputs
4)
DQS[8:0]
SDRAM low data strobes
A10/AP
Column Address Input for Auto-
Precharge
DM[8:0] /
DQS[17:9]
SDRAM low data mask/
high data strobes
BA[1:0]
SDRAM Bank Selects
DQS[17:0]
SDRAM differential data strobes
CK0
Clock input
(positive line of differential pair)
SCL
Serial bus clock
CK0
Clock input
(negative line of differential pair)
SDA
Serial bus data line
RAS
Row Address Strobe
SA[2:0]
slave address select
CAS
Column Address Strobe
V
DD
Power (+ 1.8 V)
WE
Read/Write Input
V
REF
I/O reference supply
CS[1:0]
Chip Selects
3)
V
SS
Ground
CKE[1:0]
Clock Enable
3)
V
DDSPD
RESET
EEPROM power supply
ODT[1:0]
Active termination control lines
1) 3)
Register and PLL control pin
2)
DQ[63:0]
Data Input/Output
NC
No connection
1) Active termination only applies to DQ, DQS, DQS and DM signals
2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the
PLL will remain synchronized with the input clock
3) CS1, ODT1 and CKE1 are used on dual rank modules only
4) Column address A11 is used on modules based on x4 organised 512Mb DDR2 components only.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T512400BF-3S 制造商:Qimonda 功能描述:
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HYB18T512800BF-3.7 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C,2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN(2x3) 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF)
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