參數(shù)資料
型號(hào): HYB39L128160AC-7.5
廠商: INFINEON TECHNOLOGIES AG
英文描述: HEX DIE SET,.100/.213/.429
中文描述: BJAWBMSpecialty DRAM的移動(dòng)RAM
文件頁數(shù): 6/49頁
文件大?。?/td> 938K
代理商: HYB39L128160AC-7.5
HYB 39L128160AC/T
128-MBit 3.3V Mobile-RAM
INFINEON Technologies
6
2003-02
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are
sampled on the rising edge of the clock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiates either the Power
Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the command to be executed by
the SDRAM.
A0 - A11
Input
Level
During a Bank Activate command cycle, A0 - A11 define
the row address (RA0 - RA11) when sampled at the rising
clock edge.
During a Read or Write command cycle, A0-A8 define the
column address (CA0 - CA8) when sampled at the rising
clock edge.
In addition to the column address, A10 (= AP) is used to
invoke autoprecharge operation at the end of the burst read
or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
BA0, BA1 Input
Level
Bank Select Inputs. Selects which bank is to be active.
DQx
Input
Output
Level
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
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