參數(shù)資料
型號: HYB39S64160AT-6
廠商: INFINEON TECHNOLOGIES AG
元件分類: DRAM
英文描述: 4M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54
封裝: 10.16 X 22.22 MM, 0.80 MM PITCH, PLASTIC, TSOP2-54
文件頁數(shù): 14/18頁
文件大?。?/td> 118K
代理商: HYB39S64160AT-6
INFINEON Technologies
5
HYB39S6416A/BT-5.5/-6/-7
64MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the most important operation commands.
Mode Register
For application flexibility, a CAS latency, a burst length, and a burst sequence can be
programmed in the SDRAM mode register. The mode set operation must be done before any
activate command after the initial power up. Any content of the mode register can be altered by re-
executing the mode set command. Both banks must be in precharged state and CKE must be high
at least one clock before the mode set operation. After the mode register is set, a Standby or NOP
command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate
the mode set operation. Address input data at this timing defines parameters to be set as shown in
the following table.
Operation
CS
RAS
CAS
WE
(L/U)DQM
Standby, Ignore RAS, CAS, WE and Address
H
X
Row Address Strobe and Activating a Bank
L
H
X
Column Address Strobe and Read Command
L
H
L
H
X
Column Address Strobe and Write Command
L
H
L
X
Precharge Command
L
H
L
X
Burst Stop Command
L
H
L
X
Self Refresh Entry
L
H
X
Mode Register Set Command
L
X
Write Enable/Output Enable
X
L
Write Inhibit/Output Disable
X
H
No Operation (NOP)
L
H
X
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