參數(shù)資料
型號(hào): HYB5117800BSJ-50-
廠商: SIEMENS AG
英文描述: 2M x 8 - Bit Dynamic RAM 2k Refresh
中文描述: 200萬× 8 -位動(dòng)態(tài)隨機(jī)存儲(chǔ)器2k刷新
文件頁數(shù): 5/23頁
文件大?。?/td> 178K
代理商: HYB5117800BSJ-50-
HYB 5(3)117800/BSJ-50/-60
2M
×
8 DRAM
Semiconductor Group
5
1998-10-01
DC Characteristics
(cont’d)
T
A
= 0 to 70
°
C,
V
SS
= 0 V,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Common Parameters
Input leakage current
(0 V
V
IH
V
CC
+ 0.3 V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V
V
OUT
V
CC
+ 0.3 V)
Average
V
CC
supply current
I
I(L)
– 10
10
μ
A
1
I
O(L)
– 10
10
μ
A
1
-50 ns version
-60 ns version
(RAS, CAS, address cycling:
t
RC
=
t
RC MIN.
)
Standby
V
CC
supply current (RAS = CAS =
V
IH
)
I
CC2
Average
V
CC
supply current, during RAS-only
refresh cycles
I
CC1
80
70
mA
mA
2, 3, 4
2, 3, 4
2
mA
-50 ns version
-60 ns version
(RAS cycling, CAS =
V
IH
,
t
RC
=
t
RC MIN.
)
Average
V
CC
supply current,
during fast page mode
I
CC3
80
70
mA
mA
2, 4
2, 4
-50 ns version
-60 ns version
(RAS =
V
IL
, CAS, address cycling:
t
PC
=
t
PC MIN.
)
Standby
V
CC
supply current
(RAS = CAS =
V
CC
– 0.2 V)
Average
V
CC
supply current, during CAS-
before-RAS refresh mode
I
CC4
25
20
mA
mA
2, 3,) 4
2, 3, 4
I
CC5
1
mA
1
-50 ns version
-60 ns version
(RAS, CAS cycling:
t
RC
=
t
RC MIN.
)
I
CC6
80
70
mA
mA
2, 4
2,) 4
Capacitance
T
A
= 0 to 70
°
C,
V
CC
= 5 V
±
10 %,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10)
C
I1
C
I2
C
IO
5
pF
Input capacitance (RAS, CAS, WE, OE)
7
pF
I/O capacitance (I/O1 to I/O8)
7
pF
相關(guān)PDF資料
PDF描述
HYB 3118160BSJ-50 1M×16-Bit Dynamic RAM(1M×16位 動(dòng)態(tài)RAM(快速頁面模式))
HYB 3118160BSJ-60 1M×16-Bit Dynamic RAM(1M×16位 動(dòng)態(tài)RAM(快速頁面模式))
HYB 5118160BSJ-50 1M×16-Bit Dynamic RAM(1M×16位 動(dòng)態(tài)RAM(快速頁面模式))
HYB 5118160BSJ-60 1M×16-Bit Dynamic RAM(1M×16位 動(dòng)態(tài)RAM(快速頁面模式))
HYB5118160BSJ-50- 1M x 16-Bit Dynamic RAM 1k Refresh
相關(guān)代理商/技術(shù)參數(shù)
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