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參數(shù)資料
| 型號： | HYB514405BJ |
| 廠商： | SIEMENS AG |
| 英文描述： | 1M x 4-Bit Dynamic RAM |
| 中文描述： | 100萬× 4位動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 1361K |
| 代理商： | HYB514405BJ |
Semiconductor Group
10
HYB 514405BJ/BLJ-50/-60/-70
1M x 4 EDO - DRAM
Notes:
1) All voltages are referenced to
V
SS
.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS =
V
il
. In case of
I
CC4
it can be changed once or less during
a hyper page mode (EDO) cycle
5) An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume
t
T
= 2 ns.
7)
V
IH
(min.)
and
V
IL (max.)
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
IH
and
V
IL
.
8) Measured with the specified current load and 100 pF at
V
= 0.8 V and
V
oh
= 2.0 V. Access time is determined
by the latter of
t
RAC
,
t
CAC
,
t
AA
,
t
CPA
,
t
OEA
.
t
CAC
is measured from tristate.
9) Operation within the
t
RCD (max.)
limit ensures that
t
RAC (max.)
can be met.
t
RCD (max.)
is specified as a reference point
only. If
t
RCD
is greater than the specified
t
RCD (max.)
limit, then access time is controlled by
t
CAC
.
10) Operation within the
t
RAD (max.
)
limit ensures that
t
RAC (max.)
can be met.
t
RAD (max.)
is specified as a reference point
only. If
t
RAD
is greater than the specified
t
RAD (max.)
limit, then access time is controlled by
t
AA
.
11) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12)
t
,
t
define the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels.
t
OFF
is referenced from the rising edge of RAS or CAS, whichever occurs
last.
13) Either
t
DZC
or
t
DZO
must be satisfied.
14) Either
t
CDD
or
t
ODD
must be satisfied.
15)
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If
t
>
t
, the cycle is an early write cycle and data out pin will remain
open-circuit (high impedance) through the entire cycle; if
t
RWD
>
t
RWD (min.)
,
t
CWD
>
t
CWD (min.)
and
t
AWD
>
t
AWD (min.)
,
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB514405BJ-60 | RES 1.3K-OHM 1% 0.063W 200PPM THICK-FILM SMD-0402 5K/REEL-7IN-PA |
| HYB514405BJ-50 | 1M x 4-Bit Dynamic RAM |
| HYB514405BJL-50 | 1M x 4-Bit Dynamic RAM |
| HYB514405BJL-60 | 1M x 4-Bit Dynamic RAM |
| HYB514405BJL-70 | 1M x 4-Bit Dynamic RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB514405BJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-Bit Dynamic RAM |
| HYB514405BJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-Bit Dynamic RAM |
| HYB514405BJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-Bit Dynamic RAM |
| HYB514405BJL-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-Bit Dynamic RAM |
| HYB514405BJL-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 4-Bit Dynamic RAM |
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