參數(shù)資料
型號: HYE18P32160AC
廠商: INFINEON TECHNOLOGIES AG
英文描述: 32M Synchronous Burst CellularRAM
中文描述: 32M的同步突發(fā)的CellularRAM
文件頁數(shù): 35/53頁
文件大小: 1426K
代理商: HYE18P32160AC
Data Sheet
35
V2.0, 2003-12-16
HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
Figure 18
Asynchronous Write - UB, LB Controlled (OE =
V
IH
or
V
IL
, CRE =
V
IL
)
The programming of control register in SRAM-type mode is performed in the similar manner as asynchronous write
except CRE being held high during the operation. Note that CRE has to meet set-up (
t
CRES
) and hold time (
t
CREH
)
of valid state (= High) in reference to WE falling and rising edge, respectively. ADV may be kept low for entire
operation. CS should toggle at the end of the operation to get ready for following access.
Figure 19
Asynchronous Write to Control Register (OE =
V
IH
or
V
IL
)
Don't Care
A20-A0
ADDRESS
CS
WE
UB, LB
DQx OUT
t
CW
t
WC
t
AS
t
WP
t
BW
Data In Valid
DQx IN
t
DW
t
DH
High-Z
t
BLZ,
t
LZ
t
WHZ
ADV
t
BPH
t
WR
t
AW
t
VPH
t
VS
Don't Care
A20-A0
OPCODE
CS
WE
UB, LB
DQx OUT
t
CW
t
WR
t
WC
t
WP
t
AW
DQx IN
t
AS
t
CREH
t
CRES
t
LZ,
t
BLZ
t
WHZ
High-Z
A19
CRE
ADV
t
VPH
0(RCR), 1(BCR)
High-Z
t
WPH
t
AW
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