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參數(shù)資料
| 型號： | HYM364020S |
| 廠商： | SIEMENS AG |
| 英文描述： | 4M x 36-Bit Dynamic RAM Module |
| 中文描述： | 4米× 36位動態(tài)隨機存儲器模塊 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 53K |
| 代理商： | HYM364020S |
Semiconductor Group
9
HYM 364020S/GS-60
4M
×
36-Bit
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less
during a fast page mode cycle (tPC).
5) An initial pause of 200 μs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with a load equivalent to 2 TTL loads and 100 pF.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11)Either tRCH or tRRH must be satisfied for a read cycle.
12)tOFF (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to
output voltage levels
.
13)tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics
only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high
impedance) through the entire cycle.
14)These parameters are referenced to the CAS leading edge.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYM364020S-60 | 4M x 36-Bit Dynamic RAM Module |
| HYM364025S | 4M x 36-Bit EDO - DRAM Module |
| HYM364025S-50 | 4M x 36-Bit EDO - DRAM Module |
| HYM364025S-60 | 4M x 36-Bit EDO - DRAM Module |
| HYM364025GS-50 | 4M x 36-Bit EDO - DRAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYM364020S-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 36-Bit Dynamic RAM Module |
| HYM364020S-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Page Mode DRAM Module |
| HYM364025GS-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 36-Bit EDO - DRAM Module |
| HYM364025GS-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 36-Bit EDO - DRAM Module |
| HYM364025S | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 36-Bit EDO - DRAM Module |
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