參數(shù)資料
型號: HYM364025GS-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 4M x 36-Bit EDO - DRAM Module
中文描述: 4M X 36 EDO DRAM MODULE, 50 ns, SMA72
封裝: SIMM-72
文件頁數(shù): 6/10頁
文件大小: 55K
代理商: HYM364025GS-50
Semiconductor Group
6
HYM 364025S/GS-50/-60
4M
×
36-Bit EDO-Module
DC Characteristics
1)
(cont’d)
Capacitance
T
A
= 0 to 70 °C,
V
CC
= 5 V
±
10 %,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
Test
Condition
min.
max.
Average
V
CC
supply current
during hyper page mode (EDO)
(RAS =
V
IL
, CAS, address cycling,
t
HPC
=
t
HPC
min)
50 ns - Version
60 ns - Version
I
CC4
840
680
mA
mA
2) 3) 4)
Standby
V
CC
supply current
(RAS = CAS =
V
CC
– 0.2 V)
Average
V
CC
supply current
during CAS-before-RAS refresh mode
(RAS, CAS cycling,
t
RC
=
t
RC
min)
I
CC5
8
mA
1)
50 ns - Version
60 ns - Version
I
CC6
1240
1120
mA
mA
2) 4)
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10, WE)
C
I1
C
I2
C
I3
C
IO1
75
pF
Input capacitance (RAS0, RAS2)
45
pF
Input capacitance (CAS0 - CAS3)
25
pF
I/O capacitance
(DQ0-DQ7,DQ9-DQ16,DQ18-DQ25,DQ27-DQ34)
15
pF
I/O capacitance (DQ8,DQ17,DQ26,DQ35)
C
IO2
25
pF
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