參數(shù)資料
型號(hào)： HYMA6V16733F14HGTG
英文描述： 16Mx72|3.3V|45|x18|FP/EDO DRAM - 128MB Buffered DIMM
中文描述： 16Mx72 | 3.3 | 45 | x18 |計(jì)劃生育/ EDO公司的DRAM - 128MB的緩沖DIMM
文件頁(yè)數(shù)： 11/28頁(yè)
文件大?。?/td> 494K
代理商： HYMA6V16733F14HGTG
HYMA6V16730E14HGTG
Rev.0.1/Apr.01
19. When output buffers are enabled once, sustain the low impedence state until valid data is obtained.
when output buffer is turned on and off within a very short time, generally it causes large Vcc/Vss line
noise, which causes to degrade V
IH
min / V
IL
max level
20. t
HPC
(min) can be achieved during a series of EDO mode early write cycles or EDO mode read cycels
If both write and read operation are mixed in a EDO mode, /RAS cycle[EDO mode mix cycle (1)(2)]
minimum value of /CAS cycle t
HPC
[t
CAS
+ t
CP
+ 2t
T
] become greater than the specified t
HPC
(min)
value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle
(1) and (2)
21. Data output turns off and becomes high impedance from later rising edge of /RAS and /CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of /RAS and
/CAS between t
OHR
and t
OH
and between t
OFR
and t
OFF
22. t
DOH
defines the time at which the output level go cross, V
OL
=0.8V, V
OH
=2.0V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64ms
period on the condition a) and b) below
a) Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal interval
to all refresh addresses are completed.
b) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6us after
exiting from self refresh mode
24. In case of entering from /RAS-only-refresh, It is necessary to execute CBR refresh before and after
self refresh mode according as note 23
25. For L-version, It is available to apply each 128ms and 31.2us instead of 64ms and 15.6us at note 23
26. At t
RASS
> 100us, self refresh mode is activated, and not active at t
RASS
< 10us, It is undefined within
the range of 10us < t
RASS
< 100us. For t
RASS
> 10us, It is necessary to satify t
RPS
27. XXX : H or L [ H : V
IH
(min) <= V
IN
<=V
IH
(max), L : V
IH
(min) <=V
IN
<=V
IH
(max)]
///// : Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied V
IH
or V
IL
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