參數(shù)資料
型號(hào): HYMA6V16733F14HGTG
英文描述: 16Mx72|3.3V|45|x18|FP/EDO DRAM - 128MB Buffered DIMM
中文描述: 16Mx72 | 3.3 | 45 | x18 |計(jì)劃生育/ EDO公司的DRAM - 128MB的緩沖DIMM
文件頁(yè)數(shù): 6/28頁(yè)
文件大小: 494K
代理商: HYMA6V16733F14HGTG
HYMA6V16730E14HGTG
Rev.0.1/Apr.01
6
Capacitance
( Vcc = 3.3V +/- 0.3V, TA = 25C, f = 1MHz )
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method
2. /CAS = VIH to disable Dout
AC Characteristics
(Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 19)
Test Condition
Read, Write, Read-modify-write and Refresh Cycles
Parameter
Symbol
Min.
Max
Unit
Note
Input capacitance (A0 ~ A12, B0)
CI1
-
20
pF
1
Input capacitance (/WE0, /WE2, /OE0,/OE2)
CI2
-
20
pF
1,2
Input capacitance (/RAS0, /RAS2)
CI3
-
65
pF
1,2
Input capacitance (/CAS0, /CAS4)
CI4
-
20
pF
1,2
Output capacitance (DQ0 ~ DQ71)
CI/O
-
20
pF
1, 2
Parameter
Symbol
-50
-60
Unit
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
84
-
104
-
ns
/RAS precharge time
t
RP
30
-
40
-
ns
/CAS precharge time
t
CP
8
-
10
-
ns
/RAS pulse width
t
RAS
50
10,000
60
10,000
ns
/CAS pulse width
t
CAS
8
10,000
10
10,000
ns
Row address set-up time
t
ASR
5
-
5
-
ns
Row address hold time
t
RAH
8
-
10
-
ns
Column address set-up time
t
ASC
0
-
0
-
ns
Column address hold time
t
CAH
8
-
10
-
ns
/RAS to /CAS delay time
t
RCD
12
32
14
40
ns
3
/RAS to Column address delay time
t
RAD
10
20
12
25
ns
4
/RAS hold time
t
RSH
18
-
20
-
ns
/CAS hold time
t
CSH
35
-
40
-
ns
/CAS to /RAS precharge time
t
CRP
10
-
10
-
ns
Input rise and fall times : 2ns
Input level : V
IL
/ V
IH
= 0.0 / 3.0V
Input timing reference levels
: V
IL
/ V
IH
= 0.8 / 2.0V
Output timing reference levels
: VOL / VOH = 0.8 / 2.0V
Output load : 1 TTL gate + C
L
(100pF)
(Including scope and jig)
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