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參數(shù)資料
| 型號： | HYS 64D64020GU |
| 廠商： | SIEMENS AG |
| 英文描述： | 2.5 V 186-pin Unbuffered DDR-I SDRAM Modules(2.5 V 184腳、寄存型512M位 DDR-I SDRAM 模塊) |
| 中文描述： | 2.5伏186針緩沖的DDR - 1 SDRAM的模塊（2.5伏，寄存型512M位的DDR 184腳，我內(nèi)存模塊） |
| 文件頁數(shù)： | 12/15頁 |
| 文件大小： | 164K |
| 代理商： | HYS 64D64020GU |
HYS64/72D32000GU / HYS64/72D64020GU
Unbuffered DDR-I SDRAM-Modules
Preliminary Datasheet
12
5.00
AC Characteristics (for reference only)
(values apply to the SDRAM component and do not include register, PLL, or card wiring)
(
T
A
= 0 to + 70
°
C,
V
DD
= 2.5 V ± 0.2 V)
Parameter
Symbol
-7
PC266A
-7.5
PC266B
-8
PC200
Unit
Notes
min.
max.
min.
max.
min.
max.
DQ Output Access Time from CK/
CK
t
AC
– 0.75
+ 0.75
– 0.75
+ 0.75
– 0.8
+ 0.8
ns
–
DQS Output access Time from CK/
CK
t
DQSCK
– 0.75
+ 0.75
– 0.75
+ 0.75
– 0.8
+ 0.8
ns
–
CLK High Level Width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
*tCK
–
CLK Low Level Width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
*tCK
–
Clock Period
CL = 2
t
CK
7.5
20
10
20
10
20
ns
1)
CL = 2.5
7
20
7.5
20
8
20
ns
–
CL = 3
7
20
7.5
20
8
20
ns
–
DQ and DM Input Hold Time
t
DH
t
DS
t
DIPW
0.5
–
0.5
–
0.6
–
ns
–
DQ and DM Input Setup Time
0.5
–
0.5
–
0.6
–
ns
–
DQ and DM Input Pulse Width
(for each input)
1.75
–
1.75
–
2
–
ns
–
Data-Out High-impedance from CK/
CK
t
HZ
– 0.75
+ 0.75
– 0.75
+ 0.75
– 0.8
+ 0.8
ns
–
Data-Out Low-impedance from CK/
CK
t
LZ
– 0.75
+ 0.75
– 0.75
+ 0.75
– 0.8
+ 0.8
ns
–
DQS-DQ Skew
t
DQSQ
t
QH
–
+ 0.5
–
+ 0.5
–
+ 0.6
ns
–
QH Data-Out Hold Time from DQS
tHP-0.75
–
tHP-0.75
–
tHP-1.0
–
ns
2)
Write Command to First DQS
Latching Transition
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
*
t
CK
–
DQS Input Valid Time
t
DSL,H
t
MRD
0.4
0.6
0.4
0.6
0.4
0.6
*
t
CK
–
Mode Register/Extended Mode
Register Set Cycle Time
15
–
15
–
16
–
ns
–
Write Preamble Setup Time
t
WPRES
t
WPREH
t
WPST
t
IS
t
IH
t
RPRE
0
–
0
–
0
–
ns
–
DQS Hold Time from CK/CK
0.25
–
0.25
–
0.25
–
*
t
CK
–
Write Postamble
0.4
0.6
0.4
0.6
0.4
0.6
*
t
CK
–
Input Setup Time (LVTTL inputs)
0.9
–
0.9
–
1.2
–
ns
3)
Input Hold Time (LVTTL inputs)
0.9
–
0.9
–
1.2
–
ns
3)
Read Preamble
0.9
1.1
0.9
1.1
0.9
1.1
*
t
CK
–
Read Postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
*
t
CK
–
Row Active Time
t
RAS
45
120K
45
120k
50
120K
ns
–
Row Cycle Time
R/W Operation
t
RC
65
–
65
–
70
–
ns
–
Auto Refresh
t
RFC
t
RCD
t
RP
75
–
75
–
80
–
ns
1)
RAS to CAS Delay
20
–
20
–
20
–
ns
–
Row Precharge Time
20
–
20
–
20
–
ns
–
Row Activate to Row Activate Delay
t
RRD
15
–
15
–
15
–
ns
–
Write Recovery Time
t
WR
15
–
15
–
15
–
ns
–
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PDF描述 |
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| HYS 64D32000GU | 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules(2.5 V 184腳、寄存型256M位 DDR-I SDRAM 模塊) |
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| HYS 72D64020GU | 2.5 V 186-pin Unbuffered DDR-I SDRAM Modules(2.5 V 184腳、寄存型512M位 DDR-I SDRAM 模塊) |
| HYS 64V16220GDL | 3.3V SDRAM Modules(3.3V SDRAM 模塊) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS64D64020GU-7-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?512MB (64Mx64) PC2100 2-bank? |
| HYS64D64020GU-7-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS64D64020GU-8-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?512MB (64Mx64) PC1600 2-bank? |
| HYS64D64020GU-8-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
| HYS64D64020HBDL | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules |
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