參數(shù)資料
型號: HYS 64V16220GDL
廠商: SIEMENS AG
英文描述: 3.3V SDRAM Modules(3.3V SDRAM 模塊)
中文描述: 3.3V的內(nèi)存模塊(3.3V的內(nèi)存模塊)
文件頁數(shù): 9/13頁
文件大小: 91K
代理商: HYS 64V16220GDL
HYS64V16220GDL
144 pin SO-DIMM SDRAM Modules
INFINEON Technologies
9
12.99
Notes:
1. An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
2. AC timing tests have V
il
= 0.4 V and V
ih
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V
ih
and V
il
. All AC measurements assume t
T
=1ns
with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between
0.8V and 2.0 V
..
3. If clock rising time is longer than 1ns, a time (t
T
-0.5) ns has to be added to this parameter.
4. If t
T
is longer than 1ns, a time (t
T
-1) ns has to be added to this parameter.
5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh
commands must be given to “wake-up“ the device.
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
50 pF
I/O
Measurement conditions for
tac and toh
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
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