參數(shù)資料
型號: HYS 64V32300GU
廠商: SIEMENS AG
英文描述: 3.3 V 32M × 64-Bit SDRAM Module(3.3 V 32M × 64位 同步動態(tài)RAM模塊)
中文描述: 3.3伏32M的× 64位SDRAM模塊(3.3伏32M的× 64位同步動態(tài)內(nèi)存模塊)
文件頁數(shù): 15/17頁
文件大小: 114K
代理商: HYS 64V32300GU
HYS 64/72V32300GU
SDRAM-Modules
Data Book
15
3.00
SPD-Table for PC100 Modules
Byte#
Description
SPD Entry
Value
Hex
3
80
08
04
0D
o
-
3
80
08
04
0D
o
-
3
80
08
04
0D
o
-
3
80
08
04
0D
o
-
0
1
2
3
Number of SPD Bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses
(without BS bits)
Number of Column
Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at
CL = 3
SDRAM Access Time from
Clock at CL = 3
DIMM Config
Refresh Rate/Type
128
256
SDRAM
13
4
10
0A
0A
0A
0A
5
6
7
8
9
1
64/72
0
LVTTL
10.0 ns
01
40
00
01
A0
01
40
00
01
A0
01
48
00
01
A0
01
48
00
01
A0
10
6.0 ns
60
6.0
60
60
11
12
none/ECC
Self-Refresh,
7.8
μ
s
x8
n/a/x8
00
82
00
82
02
82
02
82
13
14
SDRAM Width, Primary
Error Checking SDRAM
Data Width
Minimum Clock Delay for
Back-to-Back Random
Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
08
00
08
00
08
08
08
08
15
t
CCD
= 1 CLK
01
01
01
01
16
17
18
1, 2, 4 & 8
4
CAS
latency = 2 &3
CS
latency = 0
Write latency
= 0
non buffered/
non reg.
V
DD
tol
+/– 10%
10.0/15.0 ns
0F
04
06
0F
04
06
0F
04
06
0F
04
06
19
CS Latencies
01
01
01
01
20
WE Latencies
01
01
01
01
21
SDRAM DIMM Module
Attributes
SDRAM Device Attributes:
General
Min. Clock Cycle Time at
CAS Latency = 2
00
00
00
00
22
0E
0E
0E
0E
23
A0
F0
A0
F0
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