參數(shù)資料
型號(hào): HYS 64V32300GU
廠商: SIEMENS AG
英文描述: 3.3 V 32M × 64-Bit SDRAM Module(3.3 V 32M × 64位 同步動(dòng)態(tài)RAM模塊)
中文描述: 3.3伏32M的× 64位SDRAM模塊(3.3伏32M的× 64位同步動(dòng)態(tài)內(nèi)存模塊)
文件頁(yè)數(shù): 7/17頁(yè)
文件大?。?/td> 114K
代理商: HYS 64V32300GU
HYS 64/72V32300GU
SDRAM-Modules
Data Book
7
3.00
Notes
1. All values are shown per one SDRAM component.
2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation
frequency for -7.5 and at 100 MHz for -8 and-8A modules.
Input signals are changed once during
t
CK
, excepts for
I
CC6
and for stand-by currents when
t
CK
= infinity.
3. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 are assumed and the
V
DDQ
current is excluded.
Operating Currents per SDRAM Component
1)
T
A
= 0 to 70
o
C,
V
DD
= 3.3 V
±
0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Test
Condition
Symbol
-7.5 -8/-8A
Unit Note
max.
Operating current
t
RC
=
t
RCMIN.
,
t
CK
=
t
CKMIN.
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
I
CC1
270 210
mA
2)
Precharge stand-by current
in Power Down Mode
CS =
V
IH(MIN.)
, CKE
V
IL(MAX.)
Precharge Stand-by Current
in Non-Power Down Mode
t
CK
= min.
I
CC2P
2
2
mA
2)
CS =
V
IH (MIN.)
, CKE
V
IH(MIN.)
No operating current
t
CK
= min.
I
CC2N
25
19
mA
2)
t
CK
= min., CS =
V
IH(MIN.)
,
active state (max. 4 banks)
CKE
V
IH(MIN.)
I
CC3N
CKE
V
IL(MAX.)
I
CC3P
50
45
mA
2)
10
10
mA
2)
Burst operating current
t
CK
= min.,
Read command cycling
I
CC4
80
70
mA
2), 3)
Auto refresh current
t
CK
= min.,
Auto Refresh command cycling
I
CC5
140 130
mA
2)
Self refresh current
Self Refresh Mode, CKE = 0.2 V
I
CC6
2.5
2.5
mA
2)
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