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參數資料
| 型號： | HYS 64V4300GU |
| 廠商： | SIEMENS AG |
| 英文描述： | 3.3 V 4M × 64-Bit 1 Bank SDRAM Module(3.3 V 4M × 64-位 × 1列同步動態(tài)RAM模塊) |
| 中文描述： | 3.3伏4米× 64位一銀行內存模塊（3.3伏分× 64 -位× 1列同步動態(tài)內存模塊） |
| 文件頁數： | 8/12頁 |
| 文件大?。?/td> | 91K |
| 代理商： | HYS 64V4300GU |
HYS 64V4300GU
SDRAM-Modules
Data Book
8
12.99
Notes
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7.5
and at 100 MHz for -8 modules. Input signals are changed once during
t
CK
, excepts for
I
CC6
and
for stand-by currents when
t
CK
= infinity. All values are shown per memory component.
2. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 are assumed and the
V
DDQ
current is excluded.
3. All AC characteristics are shown for device level.
An initial pause of 100
μ
s is required after power-up. Then a Precharge All Banks command must
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
4. AC timing tests have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between
V
IH
and
V
IL
. All AC measurements assume
t
T
= 1 ns with the AC output load circuit shown in Figure below. Specified
t
AC
and
t
OH
parameters
are measured with a 50 pF only, without any resistive termination and with a input signal of 1V/
ns edge rate between 0.8 V and 2.0 V.
5. If clock rising time is longer than 1 ns, a time (
t
T
/2
0.5) ns must be added to this parameter.
6. Rated at 1.4 V.
7. If
t
T
is longer than 1 ns, a time (
t
T
1) ns must be added to this parameter.
Refresh Cycle
Refresh Period (4096 cycles)
t
REF
t
SREX
–
64
–
64
ms
Self Refresh Exit Time
1
–
1
–
CLK
10)
Read Cycle
Data Out Hold Time
t
OH
t
LZ
t
HZ
t
DQZ
3
–
3
–
ns
4)
Data Out to Low Impedance Time
0
–
0
–
ns
–
Data Out to High Impedance Time
3
7
3
8
ns
11)
DQM Data Out Disable Latency
–
2
–
2
CLK
–
Write Cycle
Data Input to Precharge
(write recovery)
t
WR
2
–
2
–
CLK
–
DQM Write Mask Latency
t
DQW
0
–
0
–
CLK
–
AC Characteristics
(cont’d)
3,4
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
DD
= 3.3 V
±
0.3 V,
t
T
= 1 ns
Parameter
Symbol
Limit Values
Unit
Note
-7.5
PC133-333
-8
PC100-222
min.
max.
min.
max.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HYS64V4300GU-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HYS64V4300GU-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HYS64V64220GBDL | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:144 pin SO-DIMM SDRAM Modules |
| HYS64V64220GBDL-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|64MX64|CMOS|DIMM|144PIN|PLASTIC |
| HYS64V64220GBDL-7.5-C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?512MB PC133 (3-3-3) 2-bank. FBGA based. End-of-Life? |
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