參數(shù)資料
型號(hào)： HYS 64V8300GU
廠商： SIEMENS AG
英文描述： 3.3 V 8M × 64-Bit × 1 Bank同步動(dòng)態(tài)DRAM Module(3.3 V 8M × 64-位 × 1列同步動(dòng)態(tài)RAM模塊)
中文描述： 3.3伏800萬× 64位× 1行同步動(dòng)態(tài)內(nèi)存（3.3伏8米× 64 -位× 1列同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 11/17頁(yè)
文件大?。?/td> 115K
代理商： HYS 64V8300GU
HYS 64/72V8300/16220GU
SDRAM-Modules
Data Book
11
12.99
Notes
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7.5
modules and at 100 Mhz for -8 modules. Input signals are changed once during
t
CK
, except for
I
CC6
and for standby currents when
t
CK
= infinity. All values are shown per memory component.
2. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 assumed and the
V
DDQ
current is excluded.
3. All AC characteristics are shown on SDRAM component level.
An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
4. AC timing tests have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between
V
IH
and
V
IL
. All AC measurements assume
t
T
= 1 ns with the AC output load circuit show. Specified
t
AC
and
t
OH
parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
5. If clock rising time is longer than 1 ns, a time (
t
T
/2 – 0.5) ns must be added to this parameter.
6. Rated at 1.4 V
7. If
t
T
is longer than 1 ns, a time (
t
T
– 1) ns has to be added to this parameter.
8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)
commands must be given to “wake-up” the device.
9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self-Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
after the Self Refresh Exit command is registered.
11.This is referenced to the time at which the output achieves the open circuit condition, not to
output voltage levels.
A Serial Presence Detect storage device—E
2
PROM—is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E
2
PROM device during module
production using a Serial Presence Detect protocol (I
2
C synchronous 2-wire bus).
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
相關(guān)PDF資料
PDF描述
HYS 64V16220GU 3.3 V 16M × 72-Bit × 2 Bank同步動(dòng)態(tài)DRAM Module(3.3 V 16M × 72-位 × 2列同步動(dòng)態(tài)RAM模塊)
HYS 72V16220GU 3.3 V 16M × 64-Bit × 2 Bank同步動(dòng)態(tài)DRAM Module(3.3 V 16M × 64-位 × 2列同步動(dòng)態(tài)RAM模塊)
HYS64D16000GDL-6-B Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:25ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes
HYS64D16001GDL-6-B 200-Pin Small Outline Dual-In-Line Memory Modules
HYS64D16001GDL-7-B 200-Pin Small Outline Dual-In-Line Memory Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS64V8301GU-7.5-C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HYS64V8301GU-7.5-C2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
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HYS64V8301GU-8-C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HYS64V8301GU-8-C2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
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