參數(shù)資料
型號(hào): HYS 64V8300GU
廠商: SIEMENS AG
英文描述: 3.3 V 8M × 64-Bit × 1 Bank同步動(dòng)態(tài)DRAM Module(3.3 V 8M × 64-位 × 1列同步動(dòng)態(tài)RAM模塊)
中文描述: 3.3伏800萬× 64位× 1行同步動(dòng)態(tài)內(nèi)存(3.3伏8米× 64 -位× 1列同步動(dòng)態(tài)內(nèi)存模塊)
文件頁數(shù): 14/17頁
文件大?。?/td> 115K
代理商: HYS 64V8300GU
HYS 64/72V8300/16220GU
SDRAM-Modules
Data Book
14
12.99
SPD-Table for PC100 Modules
Byte#
Description
SPD Entry Value
Hex
16M
×
64
-8
80
08
04
0C
8M
×
64
-8
80
08
04
0C
8M
×
72
-8
80
08
04
0C
16M
×
72
-8
80
08
04
0C
0
1
2
3
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses
(without BS bits)
Number of Column
Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d) 0
Module Interface Levels
SDRAM Cycle Time at
CL = 3
SDRAM Access time from
Clock at CL = 3
Dimm Config
Refresh Rate/Type
128
256
SDRAM
12
4
9
09
09
09
09
5
6
7
8
9
1/2
64/72
01
40
00
01
A0
01
48
00
01
A0
02
40
00
01
A0
02
48
00
01
A0
LVTTL
10.0 ns
10
6.0 ns
60
60
60
60
11
12
none/ECC
Self-Refresh,
15.6
μ
s
x8
n/a/x8
00
80
02
80
00
80
02
80
13
14
SDRAM Width, primary
Error Checking SDRAM
Data Width
Minimum Clock Delay for
Back-to-Back Random
Column Address
Burst Length Supported
08
00
08
08
08
00
08
08
15
t
CCD
= 1 CLK
01
01
01
01
16
1, 2, 4, 8 & full
page
4
CAS atency = 2 &
3
CS latency = 0
Write latency = 0
non buffered/non
reg.
V
DD
tol
±
10%
8F
8F
8F
8F
17
18
Number of SDRAM Banks
Supported CAS Latencies
04
06
04
06
04
06
04
06
19
20
21
CS Latencies
WE Latencies
SDRAM DIMM Module
Attributes
SDRAM Device Attributes
General
Min. Clock Cycle Time at
CAS Latency = 2
Max. Data Access Time
from Clock for CL = 2
01
01
00
01
01
00
01
01
00
01
01
00
22
0E
0E
0E
0E
23
10.0/12.0 ns
A0
A0
A0
A0
24
6.0/7.0 ns
60
60
60
60
相關(guān)PDF資料
PDF描述
HYS 64V16220GU 3.3 V 16M × 72-Bit × 2 Bank同步動(dòng)態(tài)DRAM Module(3.3 V 16M × 72-位 × 2列同步動(dòng)態(tài)RAM模塊)
HYS 72V16220GU 3.3 V 16M × 64-Bit × 2 Bank同步動(dòng)態(tài)DRAM Module(3.3 V 16M × 64-位 × 2列同步動(dòng)態(tài)RAM模塊)
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