參數(shù)資料
型號: HYS 72D64020GR
廠商: SIEMENS AG
英文描述: 2.5 V 184-pin Registered DDR-I SDRAM Modules(2.5 V 184腳、512M位寄存型 DDR-I SDRAM 模塊)
中文描述: 2.5伏184針注冊的DDR - 1 SDRAM的模塊(2.5伏184腳,512M的位寄存型的DDR - SDRAM內(nèi)存模塊余)
文件頁數(shù): 11/18頁
文件大?。?/td> 1072K
代理商: HYS 72D64020GR
HYS 72Dxx0x0GR
Registered DDR-I SDRAM-Modules
Target Datasheet
11
4.00
Operating, Standby and Refresh Currents (for reference only)
(values apply to one SDRAM component and do not include register and PLL)
(
T
A
= 0 to +70
°
C,
V
DD
= 2.5 V ± 0.2 V)
Parameter
Symbol Test Condition
Speed
– 7.5 – 8
90
Unit Notes
– 7
100
Operating Current
t
RC
=
t
RC(min)
,
t
CK
= min.
Active-Precharge
command without burst
operation
I
CC1
1 bank operation
CAS Latency = 2
70
mA
1), 2), 3)
1)
These parameters depend on the cycle rate and are measured with the cycle determined by the minimum
value of
t
CK
and
t
RC
.
The specified values are obtained with the output open.
Input signals are changed once during three clock cycles.
8192 refresh cycles in 64 ms.
Minimum cycle time during Auto Refresh operation (
t
REF
) is greater than minimum cycle time for Read/Write
operation.
2)
3)
Precharge Standby
Current in Power Down
Mode
I
CC2P
CKE
V
IL(max)
,
t
CK
= min.,
CS =
V
IH(min)
CKE
V
IH(min)
,
t
CK
= min.,
CS =
V
IH (min)
CKE
V
IL(max)
,
t
CK
= min.
CKE
V
IH(min)
,
t
CK
= min.,
CS =
V
IH (min)
t
CK
= min.,
Read/Write command
cycling,
Multiple banks active,
gapless data, BL = 4
t
CK
= min.,
t
RC
=
t
RFC(min)
CBR command cycling
CKE
0.2 V
20
20
20
mA
1)
Precharge Standby
Current in Non-Power
Down Mode
I
CC2N
50
45
40
mA
1), 3)
No Operating Current
(Active state: 4 bank)
I
CC3P
30
30
30
mA
1)
I
CC3N
65
60
55
mA
1), 3)
Operating Current
(Burst Mode)
I
CC4
140
120
100
mA
1), 2), 3)
Auto (CBR) Refresh
Current
I
CC5
155
135
110
mA
1), 4), 5)
4)
5)
Self Refresh Current
I
CC6
1
1
1
mA
1), 4)
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