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參數(shù)資料
| 型號： | HYS 72V128320GR-7.5 |
| 廠商： | SIEMENS AG |
| 英文描述： | 3.3V 1GB SDRAM Module(3.3V 1G位 SDRAM 模塊) |
| 中文描述： | 3.3 1GB的內(nèi)存模塊（3.3 1克位內(nèi)存模塊） |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 228K |
| 代理商： | HYS 72V128320GR-7.5 |
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
Data Book
12
1.00
Notes
1. The registered DIMM modules are designed to operate under system operating conditions
between 0-55 deg C ambient, maximum sustained bandwidth and 0 LFM airflow.
2. These parameters depend on the cycle rate. All values are measured at 133 MHz operation
frequency. Input signals are changed once during tck excepts for Icc6 and for standby currents
when tck = infinity.
3. These parameters are measured with continous data stream during read access and all DQ
toggling. CL=3 and BL=4 is assumed and the Vcc current is excluded.
4. An initial pause of 100
μ
s is required after power-up. Then a Precharge All Banks command must
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation
can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize (
t
STAB
) before
any operation can be guaranteed.
5. AC timing tests have
V
IL
= 0.8 V and
V
IH
= 2.0 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between
V
IH
and
V
IL
. All AC measurements assume
t
T
= 1 ns with the AC output load circuit shown. Specified
t
AC
and
t
OH
parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
after the Self Refresh Exit command is registered.
7. Referenced to the time at which the output achieves the open circuit condition, not to output
voltage levels.
A serial presence detect storage device - E
2
PROM 34C02 - is assembled onto the module.
Information about the module configuration, speed, etc. is written into the E
2
PROM device during
module production using a serial presence detect protocol (I
2
C synchronous 2-wire bus).
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72V128320GR-7-D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|128MX72|CMOS|DIMM|168PIN|PLASTIC |
| HYS72V128320GR-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|128MX72|CMOS|DIMM|168PIN|PLASTIC |
| HYS72V128320GR-8-C2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?1GB PC100 (2-2-2) 2-bank End-of-Life? |
| HYS72V128321GR-7.5-D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?1GB PC133 (3-3-3) 2-bank? |
| HYS72V128321GR-7-D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?1GB PC133 (2-2-2) 2-bank available 2Q02? |
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